For citations:
Cheremisinov D.I., Cheremisinova L.D. Logical gates recognition in a flat transistor circuit. Informatics. 2021;18(4):96-107. (In Russ.) https://doi.org/10.37661/1816-0301-2021-18-4-96-107
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About the Authors
Keywords
Boolean function
CMOS circuits
FPGA
Shannon expansion
VHDL
algorithm
classification
convolutional neural network
deep learning
disjunctive normal form
information security
machine learning
mathematical model
mathematical models
neural network
neural networks
physical cryptography
simulation
system of Boolean functions
two-sided boundary conditions
verification
220012, Minsk, Surganov Str 6.
The United Institute of Informatics Problems
of the National Academy of Sciences of Belarus
(UIIP NASB)
e-mail: rio@newman.bas-net.by
