Objectives. When replacing a fleet of diesel buses with a fleet of electric buses, the problem of planning the fleet composition, charging infrastructure oriented towards fast recharging at route terminals, and electric bus charging schedules is relevant. The purpose of the study is to develop models and methods for elaboration of cost-effective solutions for selecting a fleet of electric buses, charging infrastructure of this type, taking into  account a number of specific conditions. The functioning of the fleet and charging infrastructure is modeled for route terminals during the most representative period of the day, characterized by the highest passenger flow intensity and maximum energy consumption.

Methods. Methods of set theory, graph theory and mathematical programing are used. 

Results. A mathematical model has been developed for the optimization problem of a homogeneous electric bus fleet, assignment of service trips to electric buses, location and quantity of fast charging stations at route terminals, and a schedule for charging electric buses on them. The total daily cost of electric buses, charging stations, and consumed electricity has been selected as the objective function. A two-level decomposition scheme for solving the problem has been proposed, at the upper level of which the assignment of electric buses to service trips from a given set is selected, and at the lower level, the infrastructure of homogeneous charging stations of terminals and the charging schedules of electric buses on them are determined with a fixed  assignment of service trips to electric buses. A heuristic randomized algorithm has been proposed to solve the upper-level subproblem, and a mixed integer linear programming model has been developed for the lower-level subproblem.

Conclusion. The solution to the upper-level subproblem consists of selecting the assignment of electric buses to service trips from a given set. Standard solvers such as IBM ILOG CPLEX, Gurobi Optimizer can be used to solve the formulated lower-level subproblem. 

Objectives. This study provides a quantitative assessment of the impact of latent variables on regional economic activity and examines the interactions among various economic sectors and their contributions to regional growth. The analysis focuses on identifying latent factors of socio-economic development across Belarusian regions during the period 2016-2024, using factor analysis techniques and structural equation modeling (SEM).

Methods. To reduce data dimensionality and identify latent factors, exploratory factor analysis (EFA) was applied using the Principal Component Analysis (PCA) extraction method. A structural equation model was constructed using the SEMOPY library in Python to estimate relationships among the identified factors. To assess the quality of the model, standard fit indices were used:  CFI  – comparative fit index; TLI  – Tucker-Lewis index; RMSEA  – root mean square error of approximation. The values of these indices allow evaluating the degree of consistency between the model and the empirical data. The model is based on a system of  23 socio-economic indicators across 128 administrative districts and cities of regional subordination.

Results. The resulting SEM demonstrates high internal consistency and statistical reliability (CFI = 0,98;  TLI = 0,97; RMSEA = 0,04), revealing significant causal linkages between latent factors. It was established that the financial sector is a key driver of investment activity, while growth in the housing stock directly stimulates consumer demand. Negative relationships were identified between agricultural potential and financial stability, as well as between industrial development and financial sustainability.

Conclusion. The developed model is an effective analytical tool for formulating evidence-based regional policy, optimizing resource allocation, and strategic planning. Promising directions for future research include incorporating time lags, adding indicators of innovation and human potential, and applying spatial econometrics methods.

Objectives. Development of methods for design compact and efficient neural networks for image recognition tasks, as well as their hardware implementation based on FPGA.

Methods. The paper proposes the concept of a learnable two-dimensional separable transformation (LST) for designing feedforward neural networks for image recognition tasks. A feature of the LST is the sequential  processing of image rows by a fully connected layer, after which the resulting representation is processed by columns using second fully connected layer. In the proposed architecture of a feedforward neural network, the LST is considered as a feature extractor. The hardware implementation of LST-based neural network is based on the concept of in-place computing (shared memory for storing source and intermediate data), as well as using a single set of computing cores to calculate all layers of the neural network.

Results. A family of compact neural network architectures LST-1 is proposed, differing in the image  embedding size. Experiments on the classification of MNIST handwritten digits have shown the high efficiency of these models: the LST-1-28 network achieves 98.37 % accuracy with 9.5 K parameters, and the more compact LST-1-8 shows 96.53 % accuracy with 1.1 K parameters. Testing of the LST-1-28 hardware implementation  confirms the architecture's resistance to parameter quantization errors.

Conclusion. The proposed concept of a learnable two-dimensional separable transformation provides the  design of compact and efficient neural network architectures characterized by: a small number of learnable parameters, high recognition accuracy, and the regular structure of the algorithm, which makes it possible to obtain their  effective implementations based on FPGAs.

Objectives. The aim of the research is to develop and test an approach for the automatic transformation of product layout rules, formulated in natural language, into formalized machine-readable instructions to bridge the gap between business requirements and their technical implementation.

Methods. A hybrid approach is proposed in which a large language model performs the function of a semantic translator, converting a user query into a command in a specialized domain-specific language. The resulting    command is then processed by a deterministic parser based on regular expressions for validation and parameter extraction. The BLEU metric was used to evaluate the quality of the translation on a specially created dataset of 200 «query-reference» pairs. The effectiveness of the approach was compared with a baseline rule-based method.

Results. The experiment showed high accuracy in the formalization of queries compared to the baseline approach. A qualitative analysis confirmed the system's ability to interpret correctly synonyms and slang, extract implicitly specified parameters, and filter out irrelevant commands, which proves the robustness of the proposed approach. Conclusion. The conclusion is made about the viability and practical significance of the proposed approach for reducing labor intensity and increasing the efficiency of merchandising processes. The developed system      represents a foundation for creating a new generation of intelligent tools for managing retail space.

Objectives. The purpose of the study is to examine the operational characteristics of a digital circuit designed to analyze the output signal frequency of a configurable ring oscillator within a fixed measurement window. Methods. Methods of digital device synthesis and analysis were employed, including implementation on  programmable logic integrated circuits (FPGAs), fundamentals of digital circuit design, and methods for analyzing normally distributed random variables.

Results. A digital circuit for recording the period of a configurable ring oscillator, depending on the measurement time window and the value of its configuration has been developed. Experimental studies of the generated signal periods were conducted using Xilinx ZYNQ 7000 series FPGAs. It was demonstrated that upon repeated period measurements the bits of the recording counter can be categorized into three groups: group G₂: stable bits retaining constant values across all measurements; group G₁: weakly stable bits exhibiting minor distortions; group G₀: strongly unstable bits with a distortion probability approaching 1 between measurements. It was hypothesized that group G₀ represents the digitized noise component of the measured period value. Due to numerous independent factors (components within the configurable ring oscillator and digital recorder, supply voltage deviations, die and ambient temperature variations, quantization errors, etc.), it is assumed that this noise component follows a normal distribution. Analytical proof established that a normally distributed variable, quantized using multi-bit binary numbers under specific values of mathematical expectation μ and standard deviation σ , generates only two groups: G₂ and G₀. It was proven that the probability of a '1' appearing in any bit of group G₀ approaches 0,5, and the group size can be estimated as 3+ ⌊log₂ σ⌋ The bits of group G₁ can be converted to group G₂ using various methods, such as maximum likelihood estimation or by normalizing each measurement value to a theoretically justified separation into G₂ and G₀. The values of group G₂ bits can be interpreted as a response to a challenge defined by the ring oscillator circuit configuration and measurement window, forming a novel type of multi-bit Physical Unclonable Function (PUF) characterized by high stability. Conversely, the G₀ bits can serve as  single-bit sources of random variables with near-uniform distribution, providing a foundation for building random number generators.

Conclusion. The obtained results can be utilized in embedded systems for providing unclonable identification of digital devices and for random data generation. The application of a synchronous binary counter as a frequency recording circuit for a configurable ring oscillator opens new avenues for designing multibit physical unclonable function architectures with enhanced performance metrics in terms of stability, uniqueness, and randomness.

Objectives. The problem of extracting high-level structure at the level of logical elements from a  transistor-level circuit is considered. Obtaining such a representation significantly reduces the execution time of VLSI topology verification at the design stage and serves as the basis for integrated circuit redesign. The goal of the study is to develop a method and software tools for extracting blocks representing tristable elements in CMOS  circuits.

Methods. Methods for recognizing subcircuits representing tri-state elements, in particular tristable inverters, are proposed. The task is reduced to first searching for CMOS subcircuits and transmission gates subcircuits, and then for inverter structures based on them.

Results. C++ programs have been developed that implement methods for extracting three-state elements from a flat SPICE description of a transistor circuit and including descriptions of the corresponding blocks in the  hierarchical description of the generated logical network.

Conclusion. The developed programs for searching the tristable inverters are included in the program for  decompiling transistor CMOS circuits and tested as part of it on practical examples of transistor-level circuits.