1. Electronic Design Automation: Synthesis, Verification, and Test / ed. L.-T. Wang,
2. Y.-W. Chang, K.-T. Cheng. - Elsevier, 2009.
3. Gharebaghi, A.M. High-Level Test Generation from VHDL Behavioral Descriptions /
4. A.M. Gharebaghi, Z. Navabi // Proc. of VHDL Intern. Users Forum Fall Workshop. - Orlando, Florida, 2000. - P. 123-126.
5. Murray, B.T. Hierarchical Test Generation Using Precomputed Tests for Modules /
6. B.T. Murray, J.P. Hayes // Intern. Test Conf. - Washington, 1988. - P. 221-229.
7. Goloubeva O. High-level test generation for hardware testing and software validation /
8. O. Goloubeva, M. Sonza Reorda, M. Violante // Workshop of High-Level Design Validation and Test. - San Francisco, California, 2003. - P. 143-148.
9. Zolotorevich, L.A. Development of tests for VLSI circuit testability at the upper design levels / L.A. Zolotorevich, A.V. Il'inkova // Automation and Remote Control. - 2010. - Vol. 71, iss. 9. - P. 1888-1898.
10. Vallerio, K.S. Task graph extraction for embedded system synthesis / K.S. Vallerio, N.K. Jha // Proc. of IEEE Conf. on VLSI Design. - Portland, Oregon, 2003.
11. Larrabee, T. Test pattern generation using Boolean satisfiability / T. Larrabee // IEEE Trans. Computer-Aided Design. - 1992. - Vol. 11, № 1. - P. 4-15.
12. Новиков, Д.Я. Верификация функциональных описаний с неопределенностью на основе парафазного представления булевых функций / Д.Я. Новиков, Л.Д. Черемисинова // Информатика. - 2010. - № 3. - С. 54-62.
13. Test Pattern Generation using Boolean Proof Engines / R. Drechsler [et al.]. - Springer, Dordrecht, Heidelberg, London, New York, 2009.
14. Automatic Constraint Based Test Generation for Behavioral HDL Models / S.K. Hari [et al.] // IEEE Trans. on VLSI systems. - 2008. - Vol. 16, № 4. - P. 408-421.
15. Alizadeh, B. High level test generation without ILP and SAT Solvers / B. Alizadeh, M. Fujita // Int. Workshop on High Level Design Validation and Testing (HLDVT07). - Irvin, Ca, 2007. - P. 298-304.
16. Koo, H.-M. Functional Test Generation Using Design and Property Decomposition Techniques / H.-M. Koo, P. Mishra // ACM Transactions on Embedded Computing Systems. - 2009. - Vol. 8, № 4. - Article 32. - P. 1-32.