informИнформатикаInformatics1816-03012617-6963UIIP NASBinform-299Research ArticleЛОГИЧЕСКОЕ ПРОЕКТИРОВАНИЕLOGICAL DESIGNПОСТРОЕНИЕ ТЕСТОВ И ВЕРИФИКАЦИЯ ПОТОКОВЫХ МОДЕЛЕЙ ЦИФРОВЫХ УСТРОЙСТВ НА ЯЗЫКЕ VHDLЗолоторевичЛ. А.Белорусский государственный университетBelarus20121903201802(34)8797Copyright © Золоторевич Л.А., 20182018Золоторевич Л.А.Золоторевич Л.А.Данная работа распространяется под лицензией Creative Commons Attribution 4.0.This work is licensed under a Creative Commons Attribution 4.0 License.https://inf.grid.by/jour/article/view/299

Предлагается единый подход к верификации проектов и направленному построению тестовконтроля СБИС, представленных в потоковом виде на уровне RTL на языке VHDL с использованием арифметических, логических операторов и оператора If. Задача построения тестов и верификации проектов решается на основе КНФ-выполнимости некоторой системы булевых функций.

ReferencesElectronic Design Automation: Synthesis, Verification, and Test / ed. L.-T. Wang,Electronic Design Automation: Synthesis, Verification, and Test / ed. L.-T. Wang,Y.-W. Chang, K.-T. Cheng. – Elsevier, 2009.Y.-W. Chang, K.-T. Cheng. – Elsevier, 2009.Gharebaghi, A.M. High-Level Test Generation from VHDL Behavioral Descriptions /Gharebaghi, A.M. High-Level Test Generation from VHDL Behavioral Descriptions /A.M. Gharebaghi, Z. Navabi // Proc. of VHDL Intern. Users Forum Fall Workshop. – Orlando, Florida, 2000. – P. 123–126.A.M. Gharebaghi, Z. Navabi // Proc. of VHDL Intern. Users Forum Fall Workshop. – Orlando, Florida, 2000. – P. 123–126.Murray, B.T. Hierarchical Test Generation Using Precomputed Tests for Modules /Murray, B.T. Hierarchical Test Generation Using Precomputed Tests for Modules /B.T. Murray, J.P. Hayes // Intern. Test Conf. – Washington, 1988. – P. 221–229.B.T. Murray, J.P. Hayes // Intern. Test Conf. – Washington, 1988. – P. 221–229.Goloubeva O. High-level test generation for hardware testing and software validation /Goloubeva O. High-level test generation for hardware testing and software validation /O. Goloubeva, M. Sonza Reorda, M. Violante // Workshop of High-Level Design Validation and Test. – San Francisco, California, 2003. – P. 143–148.O. Goloubeva, M. Sonza Reorda, M. Violante // Workshop of High-Level Design Validation and Test. – San Francisco, California, 2003. – P. 143–148.Zolotorevich, L.A. Development of tests for VLSI circuit testability at the upper design levels / L.A. Zolotorevich, A.V. Il'inkova // Automation and Remote Control. – 2010. – Vol. 71, iss. 9. – P. 1888–1898.Zolotorevich, L.A. Development of tests for VLSI circuit testability at the upper design levels / L.A. Zolotorevich, A.V. Il'inkova // Automation and Remote Control. – 2010. – Vol. 71, iss. 9. – P. 1888–1898.Vallerio, K.S. Task graph extraction for embedded system synthesis / K.S. Vallerio, N.K. Jha // Proc. of IEEE Conf. on VLSI Design. – Portland, Oregon, 2003.Vallerio, K.S. Task graph extraction for embedded system synthesis / K.S. Vallerio, N.K. Jha // Proc. of IEEE Conf. on VLSI Design. – Portland, Oregon, 2003.Larrabee, T. Test pattern generation using Boolean satisfiability / T. Larrabee // IEEE Trans. Computer-Aided Design. – 1992. – Vol. 11, № 1. – P. 4–15.Larrabee, T. Test pattern generation using Boolean satisfiability / T. Larrabee // IEEE Trans. Computer-Aided Design. – 1992. – Vol. 11, № 1. – P. 4–15.Новиков, Д.Я. Верификация функциональных описаний с неопределенностью на основе парафазного представления булевых функций / Д.Я. Новиков, Л.Д. Черемисинова // Информатика. – 2010. – № 3. – С. 54–62.Новиков, Д.Я. Верификация функциональных описаний с неопределенностью на основе парафазного представления булевых функций / Д.Я. Новиков, Л.Д. Черемисинова // Информатика. – 2010. – № 3. – С. 54–62.Test Pattern Generation using Boolean Proof Engines / R. Drechsler [et al.]. – Springer, Dordrecht, Heidelberg, London, New York, 2009.Test Pattern Generation using Boolean Proof Engines / R. Drechsler [et al.]. – Springer, Dordrecht, Heidelberg, London, New York, 2009.Automatic Constraint Based Test Generation for Behavioral HDL Models / S.K. Hari [et al.] // IEEE Trans. on VLSI systems. – 2008. – Vol. 16, № 4. – P. 408–421.Automatic Constraint Based Test Generation for Behavioral HDL Models / S.K. Hari [et al.] // IEEE Trans. on VLSI systems. – 2008. – Vol. 16, № 4. – P. 408–421.Alizadeh, B. High level test generation without ILP and SAT Solvers / B. Alizadeh, M. Fujita // Int. Workshop on High Level Design Validation and Testing (HLDVT07). – Irvin, Ca, 2007. – P. 298–304.Alizadeh, B. High level test generation without ILP and SAT Solvers / B. Alizadeh, M. Fujita // Int. Workshop on High Level Design Validation and Testing (HLDVT07). – Irvin, Ca, 2007. – P. 298–304.Koo, H.-M. Functional Test Generation Using Design and Property Decomposition Techniques / H.-M. Koo, P. Mishra // ACM Transactions on Embedded Computing Systems. – 2009. – Vol. 8, № 4. – Article 32. – P. 1–32.Koo, H.-M. Functional Test Generation Using Design and Property Decomposition Techniques / H.-M. Koo, P. Mishra // ACM Transactions on Embedded Computing Systems. – 2009. – Vol. 8, № 4. – Article 32. – P. 1–32.

The authors declare that there are no conflicts of interest present.