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SYNTHESIS OF FPGA ARCHITECTURES OF BLOCK LIFTING-BASED FILTER BANKS IN QUATERNION ALGEBRA (PART 1)

Abstract

Nowadays the methodology for designing systems on a chip is based on highly parameterized IP components which provide a wide range of adjustment of costs in resources, fixed point arithmetic data formats and system performance for a specific target application. The article presents a systematic approach for synthesizing FPGA architectures of integer reversible paraunitary filter banks in quaternion algebra (Int-Q-PUBB) for L2L (lossless-to-lossy) image transformed encoding. It is shown that the basic elementary transformation of the filter bank is the operation of quaternion multiplication (Q-MUL), the block-lifting factorization of which and the distributed arithmetic on the adder are the basis of the parametrizable Q-MUL IP-component.

For citations:


Rybenkov E.V., Petrovsky N.A. SYNTHESIS OF FPGA ARCHITECTURES OF BLOCK LIFTING-BASED FILTER BANKS IN QUATERNION ALGEBRA (PART 1). Informatics. 2018;15(2):29-44. (In Russ.)

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ISSN 1816-0301 (Print)
ISSN 2617-6963 (Online)