Verification of systems with behavior parallelism on the basis of the graph of reachable states

Abstract

Considered problem of model based verification of control systems is the checking whether the system behavior satisfies the requirements fixed in the design specification The testing includes the experiments consisting in simulation of investigated system to see input-output correspondence to the model. The test sequence is generated on the basis of the model that describes the desired behavior of the system. The method to construct a test sequence for verification of hardware (or software) implementation of a control system with behavior parallelism is suggested that is based on traversal of the graph of the states that are reachable in system functioning. A method for constructing the set of reachable global states for a parallel algorithm of the control system behavior and a method to obtain the test sets are described. The description of the system functioning, which is given by the design specification, is assumed to be correct. The hardware (or software) implementation that must conform to this specification is to be verified.