Recognition of Subcircuits of Tristable Elements in CMOS VLSI
https://doi.org/10.37661/1816-0301-2025-22-4-82-93
Abstract
Objectives. The problem of extracting high-level structure at the level of logical elements from a transistor-level circuit is considered. Obtaining such a representation significantly reduces the execution time of VLSI topology verification at the design stage and serves as the basis for integrated circuit redesign. The goal of the study is to develop a method and software tools for extracting blocks representing tristable elements in CMOS circuits.
Methods. Methods for recognizing subcircuits representing tri-state elements, in particular tristable inverters, are proposed. The task is reduced to first searching for CMOS subcircuits and transmission gates subcircuits, and then for inverter structures based on them.
Results. C++ programs have been developed that implement methods for extracting three-state elements from a flat SPICE description of a transistor circuit and including descriptions of the corresponding blocks in the hierarchical description of the generated logical network.
Conclusion. The developed programs for searching the tristable inverters are included in the program for decompiling transistor CMOS circuits and tested as part of it on practical examples of transistor-level circuits.
About the Author
Л. Черемисинова
The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
Belarus
Belarus
Ljudmila D. Cheremisinova, D. Sc. (Eng.), Prof., Chief Researcher,
6, Surganova st., Minsk, 220012.
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For citations:
Recognition of Subcircuits of Tristable Elements in CMOS VLSI. Informatics. 2025;22(4):82-93. (In Russ.) https://doi.org/10.37661/1816-0301-2025-22-4-82-93
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