Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions

D. I. Cheremisinov; L. D. Cheremisinova

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Cheremisinov D.I., Cheremisinova L.D. Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions. Informatics. 2024;21(3):23-38. (In Russ.) https://doi.org/10.37661/1816-0301-2024-21-3-23-38

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This work is licensed under a Creative Commons Attribution 4.0 License.

ISSN 1816-0301 (Print)
ISSN 2617-6963 (Online)

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