Formal description model and conditions for detecting linked coupling faults of the memory devices

Objectives. The aim of the work is to develop and analyze a formal model for describing complex linked coupling faults of memory devices and to formulate the necessary and sufficient conditions for their detection. The relevance of these studies lies in the fact that modern memory devices, characterized by a large amount of stored data and manufactured according to the latest technological standards, are distinguished by the manifestation of complex types of faults in them.

Methods. The presented results are based on the classical theory and practice of march tests (March tests) of memory devices. In particular, the paper uses formal mathematical models for describing memory faults and shows their limitations for representing complex linked coupling faults. The main idea of the approach proposed by the authors is based on the use of a new formal description of such faults, the key element of which is the introduction of roles performed by the cells involved in the fault.

Results. Three main roles are defined that cells of the complex linked coupling faults perform, namely the role of the aggressor (A), the role of the victim (V), as well as the role of both the victim and the aggressor (B), performed by two cells simultaneously in relation to each other. It is shown that the scenario for the implementation of the roles of memory failure cells is determined by the marching test used, and, first of all, by the address sequence used to access the cells. The procedure for setting a formal model of a linked fault is given, the basis of which is the roles performed by the cells included in the fault and the scenario specified by the test. A statement is given that determines, on the basis of a new formal description of linked coupling faults, the necessary and sufficient conditions for the detection of such faults. The presence of undetectable linked coupling faults is shown, and the conditions for their detection are formulated using multiple March tests. The conducted experimental studies have confirmed the validity of the formulated provisions of the article. On the basis of the classical example of a linked coupling fault, the fulfillment of necessary and sufficient conditions for its detection by a single march test is shown.

Conclusion. The results of the research confirm that the proposed formal mathematical model for describing linked coupling faults makes it possible to determine their detection by marching tests. Within the framework of the proposed model, the necessary and sufficient conditions for detecting linked coupling faults by marching tests that detect single coupled faults are determined.

1. Lee K., Kim J., Baeg S. Coverage re-evaluation of memory test algorithms with physical memory characteristics. IEEE Access, 2021, vol. 9, pp. 124632–124639.

2. Goor A. J. Testing Semiconductor Memories, Theory and Practice. Chichester, UK, John Wiley & Sons, 1991, 536 p.

3. Yarmolik S. V., Zankovich А. P., Ivaniuk А. А. Marshevue testu dlya testirovaniya OZU. March Tests for Memory Testing. Saarbrücken, Germany, LAP Lambert Academic Publishing, 2012, 302 p. (In Russ.).

4. Yarmolik V. N., Murashko I. А., Kummert А., Ivaniuk А. А. Nerazrushayuschee testirovanie zapominayuschih ustroistv. Non-Destructive Storage Testing. Minsk, Bestprint, 2005, 230 р. (In Russ.).

5. Cascaval P., Bennett S. Efficient march test for 3-coupling faults in random access memories. Microprocessors and Microsystems, 2001, vol. 24, no. 10, pp. 501–509.

6. Caşcaval P., Caşcaval D. March test algorithm for unlinked static reduced three-cell coupling faults in random-access memories. Microelectronics Journal, 2019, vol. 93, iss. C, art. 104619.

7. Cockburn B. E., Sat Y. F. Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs. Proceedings of the IEEE International Test Conference, Washington, DC, USA, 21–25 October 1995. Washington, DC, USA, 1995, pp. 23–32.

8. Cockburn B. E. Deterministic tests for detecting single V-coupling faults in RAMs. Journal of Electronic Testing: Theory and Applications, 1994, vol. 5, no. 1, pp. 91–113.

9. Mikitjuk V. G., Yarmolik V. N. RAM testing algorithm for detection multiple linked faults. Proceedings of the 1996 European Design and Test Conference (ED&TC’96), Paris, France, 11–14 March 1996. Paris, France, 1996, pp. 435–440.

10. Goor A. J., Gaydadjiev G. N., Yarmolik V. N., Mikitujk V. G. March LR: a test for realistic linked faults. Proceedings of the 14 th VLSI Test Symposium, Princeton, NJ, USA, 28 April – 01 May 1996. Princeton, NJ, USA, 1996, pp. 272–280.

11. Goor A. J., Gaydadjiev G. N., Yarmolik V. N., Mikitujk V. G. March LA: a test for linked memory faults. Proceedings of the 1997 European Design and Test Conference (ED&TC’97), Paris, France, 17–20 March 1997. Paris, France, 1997, p. 627.

12. Ying L. W., Hussin R., Ahmad N., Fook L. W., Jidin A. Z. Modified March MSS for unlinked dynamic faults detection. Proceedings of the IEEE 20th Student Conference on Research and Development (SCOReD), Bangi, Malaysia, 08–09 November 2022. Bangi, Malaysia, 2022, pp. 68–72.

13. Chou C.-W., Chen Y.-X., Li J.-F. Testing inter-word coupling faults of wide I/O DRAMs. Proceedings of the 2015 IEEE 24th Asian Test Symposium, Mumbai, India, 22–25 November 2015. Mumbai, India, 2015, pp. 22–25.

14. Manasa R., Verma R., Koppad D. Implementation of BIST technology using March-LR algorithm. Proceedings of the 2019 4th International Conference on Recent Trends on Electronics Information Communication & Technology (RTEICT), Bangalore, India, 17–18 May 2019. Bangalore, India, 2019, pp. 1208–1212.

15. Jidin A. Z., Hussin R., Mispan M. S., Lee W. F., Zakaria N. A. Implementation of minimized March SR algorithm in a memory BIST controller. Journal of Engineering and Technology, 2022, vol. 13, no. 2, pp. 1−14.

16. Yarmolik V. N. Kontrol' i diagnostika cifrovyh ustrojstv jelektronno-vychislitel'nyh mashin. Monitoring and Diagnostics of Digital Devices of Electronic Computers. Minsk, Nauka i tehnika, 1988, 240 р. (In Russ.).

17. Sokol B., Yarmolik S. V. Address sequence for march tests to detect pattern sensitive faults. Proceedings of 3rd IEEE International Workshop on Electronic Design Test and Applications (DELTA’06), Kuala Lumpur, Malaysia, 17–19 January 2006. Kuala Lumpur, Malaysia, 2006, рр. 354–357.

18. Sokol B., Mrozek I., Yarmolik V. N. Impact of the address changing on the detection of pattern sensitive faults. Information Processing and Security Systems. London, Springer Science + Business Media, Inc., 2005, рр. 217–226.

19. Yarmolik S. V. Address sequences and backgrounds with different Hamming distance for multiple run March tests. IEEE International Journal of Applied Mathematics and Computer Science, 2008, vol. 18, no. 3, рр. 329−339.

20. Mrozek I. Multi-run Memory Tests for Pattern Sensitive Faults. Cham, Springer International Publishing AG, 2019, 135 p.

21. Yarmolik V. N., Levantsevich V. A., Demenkovets D. V., Mrozek I. Construction and application of march tests for pattern sensitive memory faults detection. Informatika [Informatics], 2021, vol. 18, no. 1, pp. 25–42 (In Russ.).