2D physically unclonable functions of the arbiter type

Objectives. The problem of constructing a new class of physically unclonable functions of the arbiter type (APUF) is being solved, based on the difference in delay times for the inputs of numerous modifications of the base element, due to both an increase in the number of inputs and the topology of their connection. Such an  approach allows building two-dimensional physically unclonable functions (2D-APUF), in which, unlike  classical APUF, the challenge generated for each basic element selects a pair of paths not from two possible, but from a larger number of them. The relevance of such a study is associated with the active development of  physical cryptography. The following goals are pursued in the work: the construction of the basic elements of the APUF and their modifications, the development of a methodology for constructing 2D-APUF.

Methods. The methods of synthesis and analysis of digital devices are used, including those based on  programmable logic integrated circuits, the basics of Boolean algebra and circuitry. 

Results. It is shown that the classical APUF uses a standard basic element that performs two functions,  namely, the function of choosing a pair of paths Select and the function of switching paths Switch, which, due to their joint use, allow achieving high performance. First of all, this concerns the stability of the APUF functioning, which is characterized by a small number of challenge, for which the response randomly takes one of two  possible values 0 or 1. Modifications of the base element in terms of the implementations of its Select and Switch functions are proposed. New structures of the base element are presented in which the modifications of their  implementations are made, including in terms of increasing the number of pairs of paths of the base element from which one of them is selected by the challenge, and the configurations of their switching. The use of  various basic elements makes it possible to improve the main characteristics of APUF, as well as to break the regularity of their structure, which was the main reason for hacking APUF through machine learning. 

Conclusion. The proposed approach to the construction of physically unclonable 2D-APUF functions, based on the difference in signal delays through the base element, has shown its efficiency and promise. The effect of improving the characteristics of such PUFs has been experimentally confirmed with noticeable improvement in the stability of their functioning. It seems promising to further develop the ideas of constructing two-dimensional physically unclonable functions of the arbiter type, as well as experimental study of their characteristics, as well as resistance to various types of attacks, including using machine learning.

1. Pappu R. Physical One-Way Functions: PhD Thesis in Media Arts and Sciences. Cambridge, Massachusetts Institute of Technology, 2001, 154 p.

2. Gassend B., Clarke D., Dijk M. S., Devadas S. Silicon physical random functions. Proceedings of the 9th Computer and Communications Security Conference (CCS’02), Washington, DC USA, 18-22 November 2002. Washington, 2002, pp. 148-160.

3. Tuyls P., Skoric B., Kevenaar T. Security with Noisy Data: On Private Biometrics, Secure Key Storage and Anti-Counterfeiting. In P. Tuyls (ed.). New York, Springer, 2007, 339 p.

4. Rührmair U., Busch H., Katzenbeisser S. Strong PUFs: models, constructions, and security proofs. Towards Hardware-Intrinsic Security. In A.-R. Sadeghi, D. Naccache (eds.). Berlin, Heidelberg, Springer, 2010, pp. 79-96.

5. Skoric B., Tuyls P., Ophey W. Robust key extraction from physical uncloneable functions. Proceedings of International Conference Applied Cryptography and Network Security, New York, USA, 7-10 June 2005. New York, 2005, pp. 407-422.

6. Lee J. W., Lim D., Gassend B., Suh G. E., …, Devadas S. A technique to build a secret key in integrated circuits for identification and authentication applications. Proceedings of International Symposium VLSI Circuits (VLSI’04), Honolulu, Hawaii, USA, 7-19 June 2004. Honolulu, 2004, rr. 176-179.

7. Lim D., Lee J. W., Gassend B., Suh G. E., …, Devadas S. Extracting secret keys from integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, vol. 13, no. 10, pp. 1200-1205.

8. Maes R., Van Herrewege A., Verbauwhede I. PUFKY: A fully functional PUF-based cryptographic key generator. Proceedings of 14th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2012), Leuven, Belgium, 9-12 September 2012. Leuven, 2012, pp. 302-319.

9. Yarmolik V. N., Vashinko Y. G. Physical unclonable functions. Informatika [Informatics], 2011, no. 2(30), pp. 92-103 (In Russ.).

10. Ivaniuk A. A., Zalivaka S. S. Physical cryptography and security of digital devices. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2019, no. 2(120), pp. 50-58 (In Russ.).

11. Martvel G. A., Chuprakov F. M., Nedostoev K. A., Baburin N. S. Software implementation of physically non-cloneable functions. Trudy Moskovskogo fiziko-tehnicheskogo instituta [Proceedings of Moscow Institute of Physics and Technology], 2020, vol. 12, no. 2, pp. 55-63 (In Russ.).

12. Rührmair U., Sölter J., Sehnke F. On the foundations of Physical Unclonable Functions. IACR Cryptology ePrint Archive, 2009, vol. 2009, 20 p.

13. Delvaux J., Verbauwhede I. Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise. Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Austin, TX, USA, 2-3 June 2013. Austin, 2013, pp. 137-142.

14. Rührmair U., Sölter J., Sehnke F., Xu X., Mahmoud A., …, Devadas S. PUF modeling attacks on simulated and silicon data. IEEE Transactions on Information Forensics and Security, 2013, vol. 11, no. 8, pp. 1876-1891.

15. Xu X., Burleson W., Holcomb D. E. Using statistical models to improve the reliability of delay-based PUFs. Proceedings of IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, 11-13 July 2016. Pittsburgh, 2016, pp. 547-552.

16. Agarwal A., Blaauw D., Zolotov V. Statistical timing analysis for intra-die process variations with spatial correlations. Proceedings of International Conference on Computer Aided Design (ICCAD03), San Jose, CA, USA, 9-13 November 2003. San Jose, 2003, pp. 900-907.

17. Klybik V. P., Zalivaka S. S., Ivaniuk A. A. Reliability enhancement method for "arbiter" physicaly unclonable function. Informatika [Informatics], 2017, no. 1(53), pp. 31-43 (In Russ.).

18. Yarmolik V. N., Ivaniuk A. A., Shynkevich N. N. Physically unclonable functions with controlled propagation delay. Informatika [Informatics], 2022, vol. 19, no. 1, pp. 32−49 (In Russ.).

19. Morozov S., Maiti A., Schaumont P. An analysis of delay based PUF implementations on FPGA. Proceedings of International Symposium on Applied Reconfigurable Computing: Tools and Applications (ARC 2010), Los Angeles, CA, US, 25-27 March 2010. Los Angeles, 2010, pp. 382-387.

20. Jin C., Herder C., Ren L., Nguyen P. H., Fuller B., …, Dijk M. van. FPGA implementation of a cryptographically-secure PUF based on learning parity with noise. Cryptography, 2017, vol. 23, no. 1, pp. 1-20.

21. Gu C., Hanley N., O’neil M. Improved reliability of FPGA-based PUF identification generator design. ACM Transactions on Reconfigurable Technology and Systems, 2017, vol. 10, no. 3, pp. 1-23.

22. Kumar A., Tripathi S. L., Mishra R. METAPUF a challenge response pair generator. Periodicals of Engineering and Natural Sciences (PEN), 2018, vol. 2, no. 6, pp. 58-63.

23. Ozturk E., Hammouri G., Sunar B. Physical unclonable function with tristate buffers. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, Washington, USA, 18-21 May 2008. Seattle, 2008, pp. 3194-3197.

24. Böhm C., Hofer M. Physical Unclonable Functions in Theory and Practice. New York, Springer Science + Business Media, 2013, 270 p.

25. Yarmolik V. N., Ivaniuk A. A. Arbiter physical unclonable functions with asymmetric pairs of paths. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2022, vol. 20, no. 4, pp. 71-79 (In Russ.).

26. Machida T., Yamamoto D., Iwamoto M., Sakiyama K. A new Arbiter PUF for enhancing unpredictability on FPGA. The Scientific World Journal, 2015, vol. 2015, art. ID 864812, 13 p.

27. Zhou C., Parhi K. K., Kim C. H. Secure and reliable XOR arbiter PUF design: An experimental study based on 1 trillion challenge response pair measurements. Proceedings of 54th ACM/EDAC/IEEE Design Automation Conference (DAC 2017), Austin, TX, USA, 18-22 June 2017. Austin, 2017, pp. 1-6.

28. Maiti A., Gunreddy V., Schaumont P. A systematic method to evaluate and compare the performance of Physical Unclonable Functions. In P. Athanas, D. Pnevmatikatos, N. Sklavos (eds.). Embedded Systems Design with FPGAs. New York, Springer, 2013, pp. 245-267.