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ОБЗОР МЕТОДОВ РЕАЛИЗАЦИИ АППАРАТНЫХ ВОДЯНЫХ ЗНАКОВ В ЦИФРОВЫХ УСТРОЙСТВАХ ПРОГРАММИРУЕМОЙ ЛОГИКИ

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Аннотация

Рассматривается применение технологии водяных знаков для защиты цифровых устройств и их проектных описаний. Приводятся основные определения, модели, категории атак, характеристики, классификация водяных знаков для данной области. Описываются примеры использования аппаратных водяных знаков.

Об авторах

В. В. Сергейчик
Белорусский государственный университет информатики и радиоэлектроники
Россия


А. А. Иванюк
Белорусский государственный университет информатики и радиоэлектроники
Россия





Список литературы

1. Architecture and Design Flow for a Highly Efficient Structured ASIC / H. Man-Ho [et al.] // IEEE Transactions on VLSI Systems. – 2012. – Vol. 21, iss. 3. – P. 424–433.

2. Majzoobi, M. Introduction to hardware security and trust / M. Majzoobi, F. Koushanfar, M. Potkonjak. – N.Y. : Springer, 2011. – 427 p.

3. Qu, G. Intellectual Property Protection in VLSI Design Theory and Practice / G. Qu, M. Potkonjak. – Dordrecht : Kluwer Publishing, 2003. – 203 p.

4. System-on-Chip: Reuse and Integration / R. Saleh [et al.] // Proceedings of the IEEE. – 2006. – Vol. 94, no. 6. – P. 1050–1069.

5. Can EDA Combat the Rise of Electronic Counterfeiting? / F. Koushanfar [et al.] // Design Automation Conference. – San Francisco, USA, 2012. – P. 133–137.

6. IP DirectCores. Microsemi [Electronic Resource]. – Mode of access : http://www.microsemi.com/products/fpga-soc/design-resources/ip-cores/direct-cores. – Date of access : 5.01.2015.

7. Singh, P. A Survey of Digital Watermarking Techniques, Applications and Attacks / P. Singh, R. Chadha // Intern. J. of Engineering and Innovative Technology. – 2013. – Vol. 2, iss. 9. – P. 165–175.

8. Защелкин, К. Метод внедрения цифровых водяных знаков в аппаратные контейнеры с LUT-ориентированной архитектурой / К. Защелкин, Е. Иванова // Информатика и математические методы в моделировании. – 2013. – Т. 3, № 4. – С. 369– 384.

9. Digital Watermarking and Steganography / I. Cox [et al.]. – Burlington : Elsevier, 2008. – 587 p.

10. Torunoglu, I. Watermarking-Based Copyright Protection of Sequential Functions / I. Torunoglu, E. Charbon // IEEE J. of Solid-State Circuits. – 2000. – Vol. 35. – P. 434–440.

11. A Survey of Techniques for VLSI Protection / W. Liang [et al.] // Information Technology Journal. – 2013. – Vol. 12. – P. 2324–2332.

12. Collberg, C. Software Watermarking: Models and Dynamic Embeddings / C. Collberg, C. Thomborson // Proc. of the 26th ACM SIGPLAN-SIGACT symposium on Principles of programming languages. – N.Y., 1999. – P. 311–324.

13. Ziener, D. Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs / D. Ziener. – Erlangen, 2010. – 325 p.

14. Watermarking / T. Nie [et al.]. – Rijeka : InTech, 2012. – 276 p. 15. A Public-Key Watermarking Technique for IP Designs / A. Abdel-Hamid [et al.] // Design, Automation and Test in Europe, Proceedings. – 2005. – Vol. 1. – P. 330–335.

15. Abdel-Hamid, A. Fragile IP Watermarking Techniques / A. Abdel-Hamid, S. Tahar // NASA Conference on Adaptive Hardware and Systems. – Noordwijk, Netherlands, 2008. – P. 513– 19.

16. Bossuet, L. Automatic low-cost IP watermarking technique based on output mark insertions / L. Bossuet, B. Gal // Design Automation for Embedded System. – 2012. – Vol. 16. – P. 71–92.

17. Rashid, A. Hierarchical Watermarking for Protection of DSP Filter Cores / A. Rashid, W. Mangione-Smith, M. Podkonjak // IEEE Custom Integrated Circuits Conference. – San Diego, USA, 1999. – P. 39–42.

18. Chapman, R. IP Protection of DSP Algorithms for System on Chip Implementation / R. Chapman, T. Durrani // IEEE Transactions on Signal Processing. – 2000. – Vol. 48. – P. 854– 61.

19. Cui, A. An Improved Publicly Detectable Watermarking Scheme Based on Scan Chain Ordering / A. Cui, C.H. Chang // IEEE ISCAS, 2009. – Taipei, 2009. – P. 29–32.

20. Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Designfor- Test / W. Liang [et al.] // Radioengineering. – 2011. – Vol. 20. – P. 533–539.

21. Oliveira, A. Robust Techniques for Watermarking Sequential Circuit Designs / A. Oliveira // Design Automation Conference. – New Orleans, USA, 1999. – P. 837–842.

22. A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design / A. Cui [et al.] // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. – 2011. – Vol. 30, no. 5. – P. 678–690.

23. Zhang, L. State Encoding Watermarking for Field Authentication of Sequential Circuit Intellectual Property / L. Zhang, C. H. Chang // IEEE ISCAS, 2012. – Seoul, 2012. – P. 3013–3016.

24. Meenakumari, M. Improving the Protection of FPGA Based Sequential IP Core Designs Using Hierarchical Watermarking Technique / M. Meenakumari, G. Athisha // J. of Theoretical and Applied Information Technology. – 2014. – Vol. 63, no. 3. – P. 701–708.

25. Lach, J. Signature Hiding Techniques for FPGA Intellectual Property Protection / J. Lach, W. Mangione-Smith, M. Podkonjak // IEEE/ACM Intern. Conf. on Computer-Aided Design. – San Jose, USA, 1998. – P. 186–189.

26. Watermarking FPGA Bitfile for Intellectual Property Protection / J. Zhang [et al.] // Radioengineering. – 2012. – Vol. 21, iss. 2. – P. 764–771.

27. Lach, J. Fingerprinting Techniques for Field-Programmable Gate Array Intellectual Property Protection // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. – 2001. – Vol. 20, no. 10. – P. 1253–1261.

28. Constraint-Based Watermarking Techniques for Design IP Protection / A. Kahng [et al.] // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. – 2001. – Vol. 20, no. 10. – P. 1236–1252.

29. Cui, A. A Hybrid Watermarking Scheme for Sequential Functions / A. Cui, C. H. Chang, L. Zhang // IEEE ISCAS, 2011, Rio de Janeiro. – 2011. – P. 2333–2336.

30. Clock-Modulation Based Watermark for Protection of Embedded Processors / J. Kufel [et al.] // Design, Automation & Test in Europe Conference and Exhibition. – Dresden, 2014. – P. 1–6.

31. Marsh, C. Protecting Designs with a Passive Thermal Tag / C. Marsh, T. Kean, D. McLaren // 15th IEEE Intern. Conf. on Electronics, Circuits and Systems. – Malta, 2008. – P. 218–221. 33. Abdel-Hamid, A. IP Watermarking Techniques: Survey and Comparison / A. Abdel-Hamid, S. Tahar, E. Aboulhamid // The 3rd IEEE Intern. Workshop on System-on-Chip for Real-Time Applications. – Calgary, Canada, 2003. – P. 60–65.


Для цитирования:


Сергейчик В.В., Иванюк А.А. ОБЗОР МЕТОДОВ РЕАЛИЗАЦИИ АППАРАТНЫХ ВОДЯНЫХ ЗНАКОВ В ЦИФРОВЫХ УСТРОЙСТВАХ ПРОГРАММИРУЕМОЙ ЛОГИКИ. Информатика. 2015;(1):102-112.

For citation:


Sergeichik V.V., Ivaniuk A.A. A SURVEY OF HARDWARE WATERMARKING FOR PROGRAMMABLE LOGIC DEVICES PROTECTION. Informatics. 2015;(1):102-112. (In Russ.)

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ISSN 1816-0301 (Print)
ISSN 2617-6963 (Online)