Physically unclonable functions with controlled propagation delay

O b j e c t i v e s. The problem of constructing a new class of physically uncloneable functions (PUF) based on controlling the signal propagation delay through the elements lying on the path of its propagation is being solved. The relevance of this problem is associated with the active development of physical cryptography. For its implementation, the following goals are pursued: the construction of the basic elements of the PUF and their modifications, the development of a methodology for constructing controlled ring oscillators based on XOR elements and controlled ring oscillators based on multi-input signal switching.

M e t h o d s.  Methods  of  synthesis  and  analysis  of  digital  devices  were  used,  including  those  based  on programmable logic integrated circuits (FPGA), the basics of Boolean algebra and circuitry.

R e s u l t s. It is shown that combined PUFs based on RS-flip-flops implement the idea of controlling the signal delay by choosing a path, which is a series-connected elements selected in accordance with the PUF request. A technique for constructing an PUF with a  controlled delay through each element of the path has been developed as a development of the idea of controlling the signal delay along the path. The features and properties of PUF with controlled delay of signals of the ring oscillator type are investigated and possible solutions are shown for the case of two-bit input requests. A basic element and its modifications are proposed for constructing new PUF structures based on the control of the signal propagation delay. It is shown that the signal delay through the basic element, which is a multi-input XOR element, depends not only on the number of inputs to which the active input signal is applied, but also on fixed values of 0 or 1 at its other inputs. A new PUF structure is presented, namely, a controlled ring oscillator, its implementation is considered for the case of control by setting the inputs and their number, by which the active input signal changes.

Co n c l u s i o n. The proposed new approach to the construction of physically uncloneable functions, based on the control of signal delay through logical elements, has shown its efficiency and promise. The effect of the influence on the delays of signal propagation through the logic element, both the number of its inputs, along which the input signals change, leading to a change in the output signal, and their composition, is experimentally confirmed. It seems promising to further developing the ideas of constructing controlled ring oscillators and oscillators  with  multi-input  switching of  input  signal,  as  well  as  the  creation  of  new PUF  structures of arbiter type.

1. Pappu R. Physical One-Way Functions: PhD Thesis in Media Arts and Sciences. Cambridge, Massachusetts Institute of Technology, 2001, 154 p.

2. Gassend B., Clarke D., Dijk M. S., Devadas S. Controlled physical random functions. Proceedings of the 18th Annual Computer Security Applications Conference (ACSAC), Las Vegas, Nevada, USA, 9–13 December 2002. Las Vegas, 2002, pp. 149–160.

3. Rührmair U., Busch H., Katzenbeisser S. Strong PUFs: Models, Constructions, and Security Proofs. Towards Hardware-Intrinsic Security. In Sadeghi A.-R., Naccache D. (eds.). Berlin, Heidelberg, Springer Berlin Heidelberg, 2010, pp. 79–96.

4. Agarwal A., Blaauw D., Zolotov V. Statistical timing analysis for intra-die process variations with spatial correlations. Proceedings of the International Conference on Computer Aided Design (ICCAD03), San Jose, CA, USA, 9–13 November 2003. San Jose, 2003, pp. 900–907.

5. Böhm C., Hofer M. Physical Unclonable Functions in Theory and Practice. New York, Springer Science + Business Media, 2013, 270 p.

6. Wang Y., Wang C., Gu C., Cui Y. Theoretical analysis of delay-based PUFs and design strategies for improvement. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26–29 May 2019. Sapporo, 2019, pp. 1–5.

7. Gummalla S. An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design: Master Degree Thesis. Arizona, Arizona State University, 2011, 62 p.

8. Lee J. W., Lim D., Gassend B., Suh G., Dijk M., Devadas S. A technique to build a secret key in integrated circuits for identification and authentication applications. Proceedings of the International Symposium VLSI Circuits (VLSI’04), Honolulu, Hawaii, USA, 7–19 June 2004. Honolulu, 2004, pp. 176–179.

9. Ozturk E., Hammouri, G., Sunar B. Physical unclonable function with tristate buffers. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, Washington, USA, 18–21 May 2008. Seattle, 2008, pp. 3194–3197.

10. Chen Q., Csaba G., Lugli P., Schlichtmann U., Rührmair U. The bistable ring PUF: A new architecture for strong physical unclonable functions. Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST’11), San Diego, California, USA, 5–6 June 2011. San Diego, 2011, pp. 134–141.

11. Holcomb D. E., Burleson W., Fu K. Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Transactions on Computers, 2008, vol. 58, no. 9, pp. 1198–1210.

12. Tehranipoor F., Karimian N., Xiao K., Chandy J. DRAM-based intrinsic physically unclonable functions for system-level security and authentication. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, no. 99, pp. 1–13.

13. Yarmolik V. N., Vashinko Y. G. Physical unclonable functions. Informatika [Informatics], 2011, no. 2(30), pp. 92–103 (In Russ.).

14. Ivaniuk A. A., Zalivaka S. S. Physical cryptography and security of digital devices. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2019, no. 2(120), pp. 50–58 (In Russ.).

15. Vernikovskii E. A. Schemotehnika: uchebno-metodicheskii complex. Circuitry: Educational-methodical Complex. Minsk, Belorusskij gosudarstvennyj universitet, 2012, 200 p. (In Russ.).

16. Jouppi N. Timing analysis and performance improvement of MOS VLSI designs. IEEE Transactions on Computer-Aided Design, 1987, vol. 6, no. 4, рр. 650–665.

17. Bogdanovich M. I., Grel’ I. N., Prohorenko V. A. Tsifrovue integral’nue mikroshemy. Digital Integrated Circuits, Minsk, Belarus, 1991, 493 p. (In Russ.).

18. Ram O. V. S. S., Saurabh S. Modeling multiple-input switching in timing analysis using machine learning. IEEE Transactions on Computer, 2021, vol. 40, no. 4, pp. 723–734.

19. Rosin D. P., Rontani D., Gauthier D. J. Experiments on autonomous Boolean networks. Chaos: An Interdisciplinary Journal of Nonlinear Science, 2013, vol. 23, no. 2, pp. 1–9.

20. Park M., Rodgers J. C., Lathrop D. P. True random number generation using CMOS Boolean chaotic oscillator. Microelectronics Journal, 2015, vol. 46, no. 12, pp. 1364–1370.