Construction and application of march tests for pattern sensitive memory faults detection

The urgency of the problem of testing storage devices of modern computer systems is shown. The mathematical models of their faults and the methods used for testing the most complex cases by classical march tests are investigated. Passive pattern sensitive faults (PNPSFk) are allocated, in which arbitrary k from N memory cells participate, where k << N, and N is the memory capacity in bits. For these faults, analytical expressions are given for the minimum and maximum fault coverage that is achievable within the march tests. The concept of a primitive is defined, which describes in terms of march test elements the conditions for activation and fault detection of PNPSFk of storage devices. Examples of march tests with maximum fault coverage, as well as march tests with a minimum time complexity equal to 18N are given. The efficiency of a single application of tests such as MATS ++, March C− and March PS is investigated for different number of k ≤ 9 memory cells involved in PNPSFk fault. The applicability of multiple testing with variable address sequences is substantiated, when the use of random sequences of addresses is proposed. Analytical expressions are given for the fault coverage of complex PNPSFk faults depending on the multiplicity of the test. In addition, the estimates of the mean value of the multiplicity of the MATS++, March C− and March PS tests, obtained on the basis of a mathematical model describing the problem of the coupon collector, and ensuring the detection of all k2^k PNPSFk faults are given. The validity of analytical estimates is experimentally shown and the high efficiency of PNPSFk fault detection is confirmed by tests of the March PS type.

1. The International Technology Roadmap for Semiconductors: 2003 Edition. San Jose, CA, USA, Semiconductor Industry Association, 2003, 65 p.

2. Sharma A. K. Advanced Semiconductor Memories: Architectures, Designs, and Applications. London, John Wiley & Sons, 2003, 652 r.

3. Wang L.-T., Wu C.-W., Wen X. VLSI Test Principles and Architectures: Design for Testability. Amsterdam, Elsevier, 2006, 808 p.

4. Bushnell M. L., Agrawal V. D. Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. New York, USA, Kluwer Academic Publishers, 2000, 690 p.

5. Yarmolik V. N. Kontrol’ i diagnostika vuchislitel’nuh system. Monitoring and Diagnostics of Computer Systems. Minsk, Bestprint, 2019, 387 r. (in Russian).

6. Goor A. J. Testing Semiconductor Memories: Theory and Practice. Chichester, UK, John Wiley & Sons, 1991, 536 p.

7. Hayes J. P. Detection of pattern-sensitive faults in random access memories. IEEE Transactions on Computer, 1975, vol. 24, no. 2, pp. 150−157.

8. Anderson K. Device manufacturers test problems. Proceedings of IEEE Semiconductor Test Symposium. Cherry Hill, NJ, USA, 1972, pp. 17-26.

9. Suk D. S., Reddy S. M. Test procedures for a class of pattern-sensitive faults in semiconductor random-access memories. IEEE Transactions on Computer, 1980, vol. 29, no. 6, pp. 419−429.

10. Hayes J. P. Testing memories for single-cell pattern-sensitive fault. IEEE Transactions on Computer, 1980, vol. 29, no. 3, pp. 249−254.

11. Cheng K.-L., Tsai M.-F., Wu C. T. Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories. Proceedings of 19th IEEE VLSI Test Symposium. Marina Del Rey, CA, USA, 2001, pp. 225−237.

12. Cheng K.-L., Tsai M.-F., Wu C. T. Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, vol. 21, no. 11, pp. 284−267.

13. Cascaval P., Bennett S. Efficient march test for 3-coupling faults in random access memories. Microprocessors and Microsystems, 2001, vol. 24, no. 10, pp. 501−509.

14. Kang D.-C., Cho S.-B. An efficient built-in self-test algorithm for neighborhood pattern sensitive faults in high-density memories. Proceedings of 4th Korea-Russia International Symposium (KORUS 2000). Ulsan, South Korea, 2000, vol. 2, pp. 218-223.

15. Cockburn B. F. Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs. Proceedings IEEE International Workshop Memory Technology Design and Testing (MTDT). San Jose, CA, USA, 1995, pp. 117-122.

16. Yarmolik V. N., Mrozek I., Yarmolik S. V. Pseudoischerpuvayuchie testirovanie zapominayuschih ustroistv na baze marchevuh testov tipa March A [Pseudo-exhaustive memory testing based on March A tests]. Informatika [Informatics], 2020, no. 2(17), rr. 54-70 (in Russian).

17. Yarmolik V. N., Zankovich A. P., Ivanuok A. A. Marshevue testu dlya samotestirovaniya OZU. RAM Self-Test March Tests. Minsk, Bestprint, 2009, 270 r. (in Russian).

18. Franklin M., Saluja K., Kinoshita K. A built in self-test algorithm for row/column pattern sensitive faults in RAMs. IEEE Journal of Solid-State Circuits, 1990, vol. 25, no. 2, pp. 514−524.

19. Sfikas Y., Tsiatouhas Y. Physical design oriented DRAM neighborhood pattern sensitive fault testing. Proceedings of 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Liberec, Czech Republic, 2009, pp. 108−113.

20. Karimi F., Irrinki S., Crosbuy T., Lombardi F. Parallel testing of multi-port static random access memories. Microelectronics Journal, 2003, vol. 34, no. 1, pp. 3−21.

21. Min D.-S., Langer D. Multiple twisted data line techniques for coupling noise reduction in embedded DRAMS. IEEE Custom Integrated Circuits Conference. San Diego, CA, USA, 1999, pp. 231−234.

22. Kang D.-C., Park S. M., Cho S.-B. An efficient built-in self-test algorithm for neighborhood pattern and bit-line-sensitive faults in high density memories. ETRI Journal, 2004, vol. 26, no. 6, pp. 520−534.

23. Goor A. J. van de, Tlili I. B. S. Disturb neighborhood pattern sensitive fault. IEEE International VLSI Test Symposium. San Diego, CA, USA, 1997, pp. 37−45.

24. Yarmolik V. N., Karpovsky M. G. Transparent memory testing for pattern-sensitive faults. Proceedings of International Test Conference. Washington DC, USA, 1994, pp. 860-869.

25. Cockburn B. E., Sat Y. F. Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs. Proceedings of the IEEE International Test Conference. Washington DC, USA, 1995, pp. 23-32.

26. Yarmolik V., Klimets Y., Demidenko S. March PS(23N) test for DRAM pattern-sensitive faults. Proceedings Seventh IEEE Asian Test Symposium (ATS). Singapore, 1998, pp. 354-357.

27. Mrozek I. Multi-run Memory Tests for Pattern Sensitive Faults. Cham, Springer International Publishing AG, 2019, 135 p.

28. Nicolaidis M. Transparent BIST for RAMs. Proceedings IEEE International Test Conference. Washington DC, USA, 1992, pp. 598-607.

29. Yarmolik V. N., Murashko I. A., Kummert A., Ivaniuk A. A. Nerazrushayuschee testirovanie zapominayuschih ustroistv. Transparent Memory Testing. Minsk, Bestprint, 2005, 230 r. (in Russian).

30. Yarmolik V. N., Mrozek I., Levantsevich V. A. Pseudoischerpuvayuchie testirovanie zapominayuschih ustroistv na baze mnogokratnuch marchevuh testov [Pseudo-exhaustive memory testing based on multiple march tests]. Informatika [Informatics], 2018, no. 1(15), rr. 110-121 (in Russian).

31. Das D., Karpovsky M. G. Exhaustive and near-exhaustive memory testing techniques and their BIST implementations. Journal of Electronic Testing, 1997, vol. 10, pp. 215-229.

32. Yarmolik S. V., Yarmolik V. N. Iterativnue pochti pseudoischerpuvayuchie veroyatnostnue testu [Iterative near pseudo-exhaustive tests]. Informatika [Informatics], 2010, no. 2(26), rr. 66-75 (in Russian).

33. Niggemeyer D., Redeker M., Otterstedt J. Integration of non-classical faults in standard march tests. Proceedings IEEE International Workshop on Memory Technology, Design and Testing. San Jose, USA, 1998, pp. 91-96.

34. Yarmolik V. N., Yarmolik S. V. Adresnue posledovatel’nosti dlya mnogokratnogo testirovaniya OZU [Address sequences for multi run RAM testing]. Informatika [Informatics], 2014, no. 2(42), rr. 124-136 (in Russian).

35. Yarmolik S. V., Yarmolik V. N. Mnogokratnue nerazrushayuschie marshevue testu s izmenyaemumi adresnumi posledovatel’nostymi [Multiple non-destructive marching tests with variable address sequences]. Avtomatika i telemehanika [Automation and Remote], 2007, no. 2, rr. 21-30 (in Russian).

36. Flajolet P., Gardy D., Thimonier L. Birthday paradox, coupon collectors, caching algorithms and self-organizing search. Discrete Applied Mathematics, vol. 39, no. 3, rr. 207−229.