For citations:
Bibilo P.N., Lankevich Yu.Yu., Romanov V.I. Logical minimization for combinatorial structure in FPGA. Informatics. 2021;18(1):7-24. (In Russ.) https://doi.org/10.37661/1816-0301-2021-18-1-7-24
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About the Authors
Keywords
Boolean function
FPGA
Shannon expansion
VHDL
algorithm
classification
convolutional neural network
deep learning
disjunctive normal form
machine learning
mathematical model
mathematical models
neural network
neural networks
physical cryptography
physical one-way functions
physically unclonable functions
simulation
stationary distribution
system of Boolean functions
two-sided boundary conditions
220012, Minsk, Surganov Str 6.
The United Institute of Informatics Problems
of the National Academy of Sciences of Belarus
(UIIP NASB)
e-mail: rio@newman.bas-net.by
