For citations:
Bibilo P.N., Lankevich Yu.Yu., Romanov V.I. Logical minimization for combinatorial structure in FPGA. Informatics. 2021;18(1):7-24. (In Russ.) https://doi.org/10.37661/1816-0301-2021-18-1-7-24
Views: 596
Fullscreen
Popular articles
Vol 16, No 4 (2019)
Vol 15, No 1 (2018)
No 2 (2013)
Article Tools
Email this article (Login required)
Email the author (Login required)
Email this article (Login required)
Email the author (Login required)
About the Authors
Keywords
Boolean function
FPGA
Shannon expansion
address sequences
algorithm
boundary-value problem
classification
communicative fragment
convolutional neural network
deep learning
disjunctive normal form
logistic regression
machine learning
mathematical model
mathematical models
neural network
physical cryptography
simulation
two-sided boundary conditions
verification
wavelet transform
220012, Minsk, Surganov Str 6.
The United Institute of Informatics Problems
of the National Academy of Sciences of Belarus
(UIIP NASB)
e-mail: rio@newman.bas-net.by
