MULTIPLE FOLDING OF REGULAR STRUCTURES VIA SOLVING LOGIC EQUATIONS

Abstract

The problem under consideration is to reduce the area of the layout of regular VLSI structures by means of their multiple folding. The method of solving the key problem of multiple folding, which is implementability checking of the folding set, is suggested. The method is based on the task reduction to solving a logic equation and checking Boolean satisfiability of a conjunctive normal form.