Preview

Informatics

Advanced search

Generation of address sequences with a given switching activity

https://doi.org/10.37661/1816-0301-2020-17-1-47-62

Abstract

The relevance of testing modern computing systems and, first of all, their storage devices is shown. The studies are based on the use of a universal method for generating the address sequences with desired      properties for multiple March tests of random access memory devices.  The modification of economical method of Antonov and Saleev is used as mathematical model to form Sobol sequences. For this model a structural diagram of its hardware implementation is presented, where the storage device for storing direction numbers is used as the basis. The set of multitudes makes up the generating matrix. It is noted that the form of the generating matrix determines the basic properties of the generated sequences. Mathematical expressions are obtained that make it possible to estimate the limiting values of switching activity, both of the sequence itself and of its individual bits. A technique is proposed for the synthesis of generators of address sequences with a given switching activity both of its individual bits and of the sequence as a whole. Examples of the application of the proposed methods are considered. The applicability of the presented results to the synthesis of test sequence generators with a given switching activity for the purpose of testing storage devices and the formation of controlled random test sequences is substantiated. The results of the practical implementation of address sequence generators are presented and their main characteristics are evaluated.

About the Authors

V. N. Yarmolik
Belarusian State University of Informatics and Radioelectronics
Belarus
Vyacheslav N. Yarmolik, Dr. Sci. (Eng.), Professor


N. A. Shevchenko
Lichtenberg Gymnasium
Germany
Nikolai А. Shevchenko, Student, Member of the Scientific Community Weird Science Club,


References

1. Bushnell M. L., Agrawal V. D. Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. New York, Kluwer Academic Publishers, 2000, 690 p.

2. Wang L.-T., Wu C.-W., Wen X. VLSI Test Principles and Architectures: Design for Testability. Amsterdam, Elsevier, 2006, 808 p.

3. Yarmolik S. V., Yarmolik V. N. Mnogokratnue nerazrushayuschie marshevue testu s izmenyaemumi adresnumi posledovatel’nostymi [Multiple non-destructive marching tests with variable address sequences]. Avtomatika i telemehanika [Automation and Remote], 2007, no. 4, рр. 126–137 (in Russian).

4. Yarmolik V. N., Yarmolik S. V. Adresnue posledovatel’nosti dlya mnogokratnogo testirovaniya OZU [Address sequences for repeated testing of RAM]. Informatika [Informatics], 2014, no. 2(42), рр. 124–136 (in Russian).

5. Sharma A. K. Semiconductor Memories: Technology, Testing, and Reliability. London, John Wiley & Sons, 2002, 480 р.

6. Ugryumov E. P. Cifrovaya shemotehnika. Digital Circuitry. Saint Petersburg, BHV-Peterburg, 2010, 816 р. (in Russian).

7. Pomeranz I. An adjacent switching activity metric under functional broadside tests. IEEE Transaction on Computers, 2013, vol. 62, no. 4, pр. 404–410.

8. Pomeranz I., Reddy S. M. Switching activity as a test compaction heuristic for transition faults. IEEE Transaction VLSI Systems, 2010, vol. 18, no. 9, рр. 1357–1361.

9. Pedram M. Power minimization in IC design: principles and applications. ACM Transactions Design Automation Electronic Systems, 1996, vol. 1, рр. 3–56.

10. Cheremisinova L. D., Kirienko N. А. Optimizaciya skobochnuh predstavlenii bulevuh phunkcii s uchetom energopotrebleniya [Optimization of bracket representations of Boolean functions taking into account energy consumption]. Informatika [Informatics], 2011, no. 3(31), рр. 77–87 (in Russian).

11. Murashko I. А., Yarmolik V. N. Vstroennoe samotestirovanie. Metodu minimizacii energopotrebleniya. Built-in Self Test. Methods to Minimize Power Consumption. Saarbrücken, LAP Lambert Academic Publishing, 2012, 348 р. (in Russian).

12. Girard P., Guiller L., Landrault C., Pravossoudovitch S. A test vector ordering technique for switching activity reduction during test operation. Proceedings Ninth Great Lakes Symposium on VLSI, Ypsilanti, MI, USA, 1999. Ypsilanti, 1999, рр. 24–27.

13. Kirienko N. А., Cheremisinov D. I., Cheremisinova L. D. Optimizaciya mnogourovnevuh predstavlenii logicheskih shem glya sokrascheniya ploschadi kristala SBIS i energopotrebleniya [Optimization of multi-level representations of logic circuits to reduce VLSI chip area and power consumption]. Vestsі Natsyyanal’nai akademіі navuk Belarusі. Seryya fizika-matematychnykh navuk [Proceedings of the National Academy of Sciences of Belarus. Physics and Mathematics series], 2015, no. 2, рр. 103–111 (in Russian).

14. Wang S., Gupta S. K. An automatic test pattern generator for minimizing switching activity during scan testing activity. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, vol. 21, no. 8, рр. 954–968.

15. Wen X., Yamashita Y., Kajihara S., Wang L.-T., Saluja K. K., Kinoshita K. On low-capture-power test generation for scan testing. Proceedings VLSI Test Symposium, Palm Springs, California, USA, 2005. Palm Springs, 2005, рр. 265–270.

16. Yarmolik V. N., Yarmolik S. V. Modified gray and counter sequences for memory test address generation. Proceedings of the 13th International Conference MIXDES Design of Integrated Circuits and Systems, Gdynia, Poland, 2006. Gdynia, 2006, рр. 572–576.

17. Yarmolik V. N. Kontrol’ i diagnostika vuchislitel’nuh system. Monitoring and Diagnostics of Computer Systems. Minsk, Bestprint, 2019, 387 р. (in Russian).

18. Sobol’ I. M. Tochki, ravnomerno zapolnyayuschie mnogomernui kub. Points Uniformly Filling a Multidimensional Cube. Мoscow, Znanie, 1985, 32 р. (in Russian).

19. Antonov I. A., Saleev V. М. Ekonomichnui sposob vuchisleniya LP-posledovatel’nostei [An economical way to calculate LP sequences]. Zhurnal vychislitel'noj matematiki i matematicheskoj fiziki [Journal of Computational Mathematics and Mathematical Physics], 1979, vol. 19, no. 1, рр. 243–245 (in Russian).

20. Yarmolik S. V., Yarmolik V. N. Kvazisluchainoe testirovanie vuchislitel’nuh system [Quasi-random testing of computing systems]. Informatika [Informatics], 2013, no. 3(39), рр. 65–81 (in Russian).

21. Savage C. A survey of combinatorial Gray code. SIAM Review, 1997, vol. 39, no. 4, рр. 605–629.

22. Boyd S. Introduction to Applied Linear Algebra: Vectors, Matrices, and Least Squares. Cambridge, University Printing House, 2018, 463 p.

23. Ferreira P., Jesus B., Vieira J., Pinho A. J. The rank of random binary matrices and distributed storage applications. IEEE Communication Letters, 2013, vol. 17, no. 1, рр. 151–154.

24. Goor A. J., Kukner H., Hamdioui S. Optimizing memory BIST Address Generator implementations. Proceedings of 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Athens, Greece, 2011. Athens, 2011, рр. 572–576.

25. Du X., Mukherjee N., Cheng W. T., Reddy S. M. Full-speed field-programmable memory BIST architecture. Proceedings of IEEE International Test Conference, Austin, TX, USA, 2005. Austin, 2005, рр. 1173–1182.

26. Aswin A. M., Ganesh S. S. Implementation and validation of memory built in self-test (MBIST) –survey. International Journal of Mechanical Engineering and Technology (IJMET), 2019, vol. 10, no. 3, рр. 153–160.

27. Mrozek I., Yarmolik V. N. Iterative antirandom testing. Journal of Electronic Testing: Theory and Applications (JETTA), 2012, vol. 9, no. 3, рр. 251–266. 28.

28. Mrozek I., Yarmolik V. N. Antirandom test vectors for BIST in Hardware / Software systems. Fundamenta Informaticae, 2012, no. 119, рр. 1–23.


Review

For citations:


Yarmolik V.N., Shevchenko N.A. Generation of address sequences with a given switching activity. Informatics. 2020;17(1):47-62. (In Russ.) https://doi.org/10.37661/1816-0301-2020-17-1-47-62

Views: 900


Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.


ISSN 1816-0301 (Print)
ISSN 2617-6963 (Online)