The self-checking integrated control circuits synthesis based on the boolean complement method to "2-out-of-4" constant-weight code
Abstract
The article explores the peculiarities of self-checking integrated control circuits synthesis by the Boolean complement method based on the "2-out-of-4'' constant-weight code. The article describes the features of integrated control circuits implementation by the Boolean complement method. It is noted that it is possible to synthesize the structures of discrete devices, which have less structural redundancy than in situation of the control circuit implementation by the method of duplication. The effect in structural redundancy reducing is achieved by minimizing the complexity of the control logic block technical implementation and using checkers that are simpler in their structures than the comparator in the system of duplication. The article proposes a method of the integrated control circuit organization based on determining the values of control functions taking into account the maintenance of testability of elements of addition by modulo two in the Boolean complement block and the checker of the "2-out-of-4" code.
About the Authors
D. V. Efanov
"LocoTech-Signal" LCC, Russian University of Transport
Russian Federation
Russian Federation
Dmitry V. Efanov - Dr. Sci. (Eng.), Associate Professor, Head of the Direction of Monitoring and Diagnostic Systems at "LocoTech-Signal" LCC; Professor of "Automation, Remote Control and Communication on Railway Transport" Department RUT.
18, 3ed Rybinskaya Str., 107113, Moscow; 9, Obraztsova Str., 127994, Moscow
V. V. Sapozhnikov
Emperor Alexander I St. Petersburg State Transport University
Valery V. Sapozhnikov - Dr. Sci. (Eng.), Professor, Professor of "Automation and Remote Control on Railways" Department.
9, Moscow Ave., 190031, Saint Petersburg
Vl. V. Sapozhnikov
Emperor Alexander I St. Petersburg State Transport University
Vladimir V. Sapozhnikov - Dr. Sci. (Eng.), Professor, Professor of "Automation and Remote Control on Railways" Department.
9, Moscow Ave., 190031, Saint Petersburg
D. V. Pivovarov
Emperor Alexander I St. Petersburg State Transport University
Dmitry V. Pivovarov - Ph. D. Student, Assistant of "Automation and Remote Control on Railways" Department.
9, Moscow Ave., 190031, Saint Petersburg
References
1. Sogomonyan E. S., Slabakov E. V. Samoproveryaemye ustrojstva i otkazoustojchivye sistemy. Self-Checking Devices and Fault-Tolerance Systems. Moscow, Radio i svyaz' Publ., 1989, 208 p. (in Russian).
2. Nicolaidis M. On-line testing for VLSI: state of the art and trends. Integration, the VLSI Journal, 1998, vol. 26, iss. 1-2, pp. 197-209. doi: 10.1016/S0167-9260(98)00028-5
3. Lala P. K. Self-Checking and Fault-Tolerant Digital Design. San Francisco, Morgan Kaufmann Publishers, 2001, 216 p.
4. Gоessel M., Ocheretny V., Sogomonyan E., Marienfeld D. New Methods of Concurrent Checking. Dordrecht, Springer Science+Business Media B.V., 2008, 184 p.
5. Goessel M., Graf S. Error Detection Circuits. London, McGraw-Hill, 1994, 261 p.
6. Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V., Dmitriev V. V. Novye struktury sistem funkcional'nogo kontrolya logicheskih skhem [New structures of the concurrent error detection systems for logic circuits]. Avtomatika i telemekhanika [Automation and Remote Control], 2017, no. 2, pp. 127-143 (in Russian).
7. Borecky J., Kohlik M., Kubatova H. Parity driven reconfigurable duplex system. Microprocessors and Microsystems, 2017, vol. 52, pp. 251-260. doi: 10.1016/j.micpro.2017.06.015
8. Kundu S., Sogomonyan E. S., Goessel M., Tarnick S. Self-checking comparator with one periodic output. IEEE Transactions on Computers, 1996, vol. 45, iss. 3, pp. 379-380. doi: 10.1109/12.485577
9. Metra C., Favalli M., Ricco B. Highly testable and compact single output comparator. Proceedings of 15th IEEE VLSI Test Symposium, 27 April-1 May 1997, Monterey, CA, USA, pp. 210-215. doi: 10.1109/VTEST.1997.600272
10. Sapozhnikov V. V., Sapozhnikov Vl. V., Hristov H. A., Gavzov D. V. Metody postroeniya bezopasnyh mikroehlektronnyh sistem zheleznodorozhnoj avtomatiki. Methods of Synthesis Safety Microelectronic Railway Automation Systems. Moscow, Transport Publ., 1995, 272 p. (in Russian).
11. KubaHk P., Fiser P., Kubatova H. Fault tolerant system design method based on self-checking circuits. Proceedings of 12th International On-Line Testing Symposium 2006 (IOLTS'06). Como, Italy, 2006, pp. 185-186.
12. Theeg G., Vlasenko S. Railway Signalling & Interlocking - International Compendium. Eurailpress, 2009, 448 p.
13. Stempkovsky A. L., Telpukhov D. V., Solovjov R. A., Telpukhova N. V. Issledovanie veroyatnostnyh metodov ocenki logicheskoj uyazvimosti kombinacionnyh skhem [Probabilistic methods for reliability evaluation of combinational circuits]. Problemy razrabotki perspektivnyh mikro- i nanoehlektronnyh sistem (MES) [Problems of Development of Perspective Micro- and Nanoelectronic Systems (MES)], 2016, no. 4, pp. 121-126 (in Russian).
14. Piestrak S. J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes. Wroclaw, Oficyna Wydawnicza Politechniki Wroclavskiej, 1995, 111 p.
15. Nicolaidis M., Zorian Y. On-line testing for VLSI - a compendium of approaches. Journal of Electronic Testing: Theory and Applications, 1998, vol. 12, iss. 1-2, pp. 7-20. doi: 10.1023/A:1008244815697
16. Das D., Touba N. A. Synthesis of circuits with low-cost concurrent error detection based on bose-lin codes. Journal of Electronic Testing: Theory and Applications, 1999, vol. 15, iss. 1-2, pp. 145-155. doi: 10.1023/A:1008344603814
17. Das D., Touba N. A., Seuring M., Gossel M. Low cost concurrent error detection based on modulo weight-based codes. Proceedings of IEEE 6th International On-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, 3-5 July 2000. Palma de Mallorca, 2000, pp. 171-176. doi: 10.1109/OLT.2000.856633
18. Busaba F. Y., Lala P. K. Self-checking combinational circuit design for single and unidirectional multibit errors. Journal of Electronic Testing: Theory and Applications, 1994, vol. 5, iss. 1, pp. 19-28. doi: 10.1007/BF00971960
19. Sapozhnikov V. V., Morosov A. V., Sapozhnikov Vl. V., Gessel' M. A New design method for self-checking unidirectional combinational circuits. Journal of Electronic Testing: Theory and Applications, 1998, vol. 12, iss. 1-2, pp. 41-53. doi: 10.1023/A:1008257118423
20. Sapozhnikov Vl. V., Dmitriev A. V., Gessel' M., Sapozhnikov V. V. Self-dual parity checking - a new method for on line testing. Proceedings of 14th IEEE VLSI Test Symposium, 28 Apr. - 1 May 1996, Princeton, NJ, USA. Princeton, 1996, pp. 162-168. doi: 10.1109/VTEST.1996.510852
21. Sapozhnikov V. V., Sapozhnikov Vl. V., Dmitriev A. V., Morozov A. V., Gessel' M. Organizaciya funkcional'nogo kontrolya kombinacionnyh skhem metodom logicheskogo dopolneniya [The organization of functional control of combinational circuits by the method of complement]. Electronnoe modelirovanie [Electronic Modeling], 2002, vol. 24, no. 6, pp. 52-66 (in Russian).
22. Gessel' M., Morozov A. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Logicheskoe dopolnenie - novyj metod kontrolya kombinacionnyh skhem [Logic complement, a new method of checking the combinational circuits]. Avtomatika i telemekhanika [Automation and Remote Control], 2003, no. 1, pp. 167-176 (in Russian).
23. Gessel' M., Morozov A. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Kontrol' kombinacionnyh skhem metodom logicheskogo dopolneniya [Checking combinational circuits by the method of logic complement]. Avtomatika i telemekhanika [Automation and Remote Control], 2005, no. 8, pp. 161-172 (in Russian).
24. Sen S. K. A Self-checking circuit for concurrent checking by 1-out-of-4 code with design optimization using constraint don’t cares. National Conference on Emerging Trends and Advances in Electrical Engineering and Renewable Energy (NCEEERE 2010), Sikkim Manipal Institute of Technology. Sikkim, 2010.
25. Das D. K., Roy S. S., Dmitriev A. V., Morozov A. V., Gessel' M. Constraint don’t cares for optimizing designs for concurrent checking by 1-out-of-3 codes. Proceedings of the 10th International Workshops on Boolean Problems, Freiberg, Germany, September 2012. Freiberg, 2012, pp. 33-40.
26. Sapozhnikov V., Sapozhnikov Vl., Efanov D. Concurrent error detection of combinational circuits by the method of Boolean complement on the base of "2-out-of-4" code. Proceedings of 14th IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, 14-17 October 2016. Yerevan, 2016, pp. 126-133, doi: 10.1109/EWDTS.2016.7807677
27. Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Postroenie samoproveryaemyh struktur sistem funkcional'nogo kontrolya na osnove ravnovesnogo koda "2 iz 4" [Design of self-checking concurrent error detection systems based on "2-out-of-4" constant-weight code]. Problemy upravleniya [ControlSciences], 2017, no. 1, pp. 57-64 (in Russian).
28. Tarnick S. Design of embedded m-out-of-n code checkers using complete parallel counters. 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Crete, Greece. Crete, 2007, pp. 285-292. doi: 10.1109/IOLTS.2007.27
29. Piestrak S. Design of minimal-level PLA self-testing checkers for m-out-of-n codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1996, vol. 4, iss. 2, pp. 264-272. doi: 10.1109/92.502198
30. Sapozhnikov V. V., Sapozhnikov Vl. V. Samoproveryaemye diskretnye ustrojstva. Self-Checking Discrete Devi-ses. Saint Petersburg, Energoatomizdat Publ., 1992, 224 p. (in Russian).
31. Aksyonova G. P. Neobhodimye i dostatochnye usloviya postroeniya polnost'yu proveryaemyh skhem svertki po modulyu 2 [Necessary and sufficient conditions for design of completely checkable modulo convolution circuits]. Avtoma-tika i telemekhanika [Automation and Remote Control], 1979, no. 9, pp. 126-135 (in Russian).
32. Collection of Digital Design Benchmarks. Available at: http://ddd.fit.cvut.cz/prj/Benchmarks/ (accessed 20.02.2018).
33. Sentovich E. M., Singh K. J., Moon C., Savoj H., Brayton R. K., Sangiovanni-Vincentelli A. Sequential circuit design using synthesis and optimization. Proceedings IEEE International Conference on Computer Design: VLSI in Computers & Processors, 11-14 October 1992, Cambridge, MA, USA. Cambridge, 1992, pp. 328-333. doi: 10.1109/ICCD.1992.276282
Review
For citations:
Efanov D.V., Sapozhnikov V.V., Sapozhnikov V.V., Pivovarov D.V. The self-checking integrated control circuits synthesis based on the boolean complement method to "2-out-of-4" constant-weight code. Informatics. 2018;15(4):71-85. (In Russ.)
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