Preview

Informatics

Advanced search

Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2)

Abstract

Nowadays the methodology for designing systems on a chip is based on highly parameterized IP               (itellectual property) components which provide a wide range of adjustment of resources, fixed point arithmetic data formats, and system performance for a specific application. The article describes a flexible technology for rapid prototyping of processor architectures for integer, invertible, paraunitary filter banks in quaternion algebra (Int-Q-PUFB) based on the FPGA Q-MUL IP-component as multiplication operator for quaternions on distributed arithmetic on adders. Implementation of Int-Q-PUFB on FPGA Xilinx Zynq 7010, with 8-channel 8x24 Int-Q-PUFB has a perfect reconstruction property of the input data for a fixed point format, small hardware resource utilization and a slight delay in the pipeline compared to the known solutions for CORDIC-processors and distributed arithmetic on the memory.

For citations:


Rybenkov E.V., Petrovsky N.A. Synthesis of FPGA architectures of block lifting-based filter banks in quaternion algebra (part 2). Informatics. 2018;15(3):22-31. (In Russ.)

Views: 821


Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.


ISSN 1816-0301 (Print)
ISSN 2617-6963 (Online)