Investigation of the physically unclonable function of a configurable ring oscillator

Objectives. Design and implementation features of a Physically Unclonable Function (PUF) based on a Configurable Ring Oscillator (CRO) on FPGA platforms are examined. The study aims to evaluate the key parameters of CRO circuits and the characteristics of CRO-based PUFs under various simulation scenarios and placement configurations on FPGA dies.

Methods. Methods of synthesis and analysis of digital devices are employed, including those based on programmable logic integrated circuits, as well as the fundamentals of digital circuit design.

Results. A generalized model of a PUF based on the comparison of signal propagation delays along a pair of symmetric paths is proposed. The model includes four main stages: Generate – generating a set of symmetric paths, Select/Switch – selecting a pair of paths from the set, Measure – measuring the signal propagation delay for each selected path, and Compute – calculating the binary PUF response based on the sign of the difference between the measured delays. This model is applicable to classical PUF types such as Arbiter PUFs and Ring Oscillator PUFs, as well as their modifications. Based on the proposed model, a CRO PUF was designed and implemented on Xilinx ZYNQ 7000 FPGA devices. Experiments were conducted on both simulated models and implemented circuits to evaluate the key timing parameters of CROs and the characteristics of CRO PUFs under various simulation scenarios and two types of component placement on FPGA dies. The results demonstrated that the majority of the signal propagation delay along the selected path is determined by the delay in FPGA configurable interconnects. Regardless of the type of component placement used, this leads to the realization of predominantly asymmetric paths. The asymmetry in paths negatively impacts one of the most critical characteristics of PUFs – intra-chip uniqueness. Low intra-chip uniqueness can impose significant limitations when implementing unclonable identification schemes. However, other PUF characteristics, such as uniformity, stability, reliability, and inter-chip uniqueness, exhibited acceptably high-performance levels.

Conclusion. The conducted parametric simulation of CRO PUF circuits demonstrated its effectiveness in evaluating key PUF characteristics, such as uniformity and intra-chip uniqueness. This approach can be utilized by developers for rapid assessment of circuit quality without requiring physical implementation. Achieving acceptable inter-chip uniqueness values necessitates the development of new circuit design solutions that enable the generation of multiple symmetric paths on FPGA devices. Additionally, the measured periods of CRO circuits clearly demonstrate their uniqueness, both when implemented on the same chip and across different chips. This serves as a foundation for exploring new methods and algorithms for calculating unique PUF responses.

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