Symmetric physically unclonable functions of the arbiter type

Objectives. The problem of constructing a new class of physically unclonable functions of the arbiter type (APUF) that combines the advantages of both classical and balanced APUF is solved. The relevance of such a study is associated with the active development of physical cryptography. The following goals are pursued in the work: research and analysis of classical APUF, construction of a new mathematical model of APUF and development of a new basic element of APUF.

Methods. The methods of synthesis and analysis of digital devices are used, including those based on programmable logic integrated circuits, the basics of Boolean algebra and circuitry.

Results. It has been established that classical APUF uses a standard basic element that performs three functions, namely, the function of generating two random variables Generate, the function of choosing a pair of paths Select and the function of switching paths Switch, which are specified by one bit of the challenge. It is shown that the joint use of these functions, on the one hand, makes it possible to achieve high characteristics of the APUF, and on the other hand, leads to the formation of an asymmetric behavior of the APUF. In order to analyze the main characteristics of APUF and their ideal behavior, a new mathematical model of APUF was considered, similar to the model of random coin toss. To implement APUF functioning according to the proposed model, a new basic element was developed. It is shown that the use of the proposed basic element allows to build symmetrical physically unclonable functions (C_APUF), which differ from the classical APUF in that the Generate, Select and Switch functions of the basic element are performed by their independent components and are specified by different bits of challenge.

Conclusion. The proposed approach to the construction of symmetrical physically unclonable functions, based on the implementation of the Generate, Select and Switch functions by various components of the base element, has shown its efficiency and promise. The effect of improving the characteristics of similar C_APUF has been experimentally confirmed, and, first of all, a noticeable improvement in their probabilistic properties expressed in equal probability of responses. It seems promising to further develop the ideas of building C_APUF, experimental study of their characteristics, as well as analysis of resistance to various types of attacks, including using machine learning.

1. Pappu R. Physical One-Way Functions: PhD Thesis in Media Arts and Sciences. Cambridge, Massachusetts Institute of Technology, 2001, 154 p.

2. Gassend B., Clarke D., Dijk M. S., Devadas S. Silicon physical random functions. Proceedings of the 9th Computer and Communications Security Conference (CCS’02), Washington, DC USA, 18–22 November 2002. Washington, 2002, pp. 148–160.

3. Tuyls P., Skoric B. (eds.). Security with Noisy Data: On Private Biometrics, Secure Key Storage and Anti-Counterfeiting. New York, USA, Springer, 2007, 339 p.

4. Maes R., Van Herrewege A., Verbauwhede I. PUFKY: A fully functional PUF-based cryptographic key generator. Proceedings of 14th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2012), Leuven, Belgium, 9–12 September 2012. Leuven, 2012, pp. 302–319.

5. Skoric B., Tuyls P., Ophey W. Robust key extraction from physical uncloneable functions. Proceedings of International Conference Applied Cryptography and Network Security, New York, USA, 7–10 June 2005. New York, 2005, pp. 407–422.

6. Yarmolik V. N., Vashinko Y. G. Physical unclonable functions. Informatika [Informatics], 2011, no. 2(30), pp. 92–103 (In Russ.).

7. Suh G. E., Devadas S. Physical unclonable functions for device authentication and secret key generation. Proceedings of International Design Automation Conference, DAC 2007, San Diego, California, USA, 4–8 June 2007. San Diego, 2007, pp. 9–14.

8. Böhm C., Hofer M. Physical Unclonable Functions in Theory and Practice. New York, Springer Science + Business Media, 2013, 270 p.

9. Rührmair U., Busch H., Katzenbeisser S. Strong PUFs: models, constructions, and security proofs. Towards Hardware-Intrinsic Security. In A.-R. Sadeghi, D. Naccache (eds.). Berlin, Heidelberg, Springer, 2010, pp. 79–96.

10. Lee J. W., Lim D., Gassend B., Suh G. E., Van Dijk M., Devadas S. A technique to build a secret key in integrated circuits for identification and authentication applications. Proceedings of International Symposium VLSI Circuits (VLSI’04), Honolulu, Hawaii, USA, 7–19 June 2004. Honolulu, 2004, pp. 176–179.

11. Lim D., Lee J. W., Gassend B., Suh G. E., Van Dijk M., Devadas S. Extracting secret keys from integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, vol. 13, no. 10, pp. 1200–1205.

12. Ivaniuk A. A., Zalivaka S. S. Physical cryptography and security of digital devices. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2019, no. 2(120), pp. 50–58 (In Russ.).

13. Yarmolik V. N., Ivaniuk A. A., Shynkevich N. N. Physically unclonable functions with controlled propagation delay. Informatika [Informatics], 2022, vol. 19, no. 1, pp. 32–49 (In Russ.).

14. Xu X., Burleson W., Holcomb D. E. Using statistical models to improve the reliability of delay-based PUFs. Proceedings of IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, 11–13 July 2016. Pittsburgh, 2016, pp. 547–552.

15. Morozov S., Maiti A., Schaumont P. An analysis of delay based PUF implementations on FPGA. Proceedings of International Symposium on Applied Reconfigurable Computing: Tools and Applications (ARC 2010), Los Angeles, CA, US, 25–27 March 2010. Los Angeles, 2010, pp. 382–387.

16. Klybik V. P., Zalivaka S. S., Ivaniuk A. A. Reliability enhancement method for "arbiter" physicaly unclonable function. Informatika [Informatics], 2017, no. 1(53), pp. 31–43 (In Russ.).

17. Yarmolik V. N., Ivaniuk A. A. Arbiter physical unclonable functions with asymmetric pairs of paths. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2022, no. 4(20), pp. 71–79 (In Russ.).

18. Zhou C., Parhi K. K., Kim C. H. Secure and reliable XOR arbiter PUF design: An experimental study based on 1 trillion challenge response pair measurements. Proceedings of the 54th Annual Design Automation, Austin, TX, USA, 18 June 2017. Austin, 2017, pp. 18–22.

19. Machida T., Yamamoto D., Iwamoto M., Sakiyama K. Implementation of double arbiter PUF and its performance evaluation on FPGA. Proceedings of the 20th Asia and South Pacific Design Automation Conference, Chiba, Japan, 19 January 2015. Chiba, 2015, pp. 6–7.

20. Delvaux J., Verbauwhede I. Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise. Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Austin, TX, USA, 2–3 June 2013. Austin, 2005, pp. 137–142.

21. Rührmair U., Sölter J., Sehnke F., Xu X., Mahmoud A., …, Devadas S. PUF modeling attacks on simulated and silicon data. IEEE Transactions on Information Forensics and Security, 2013, vol. 11, no. 8, pp. 1876–1891.

22. Shamyna A. Yu., Ivaniuk A. A. Creating and balancing the paths of arbiter-based physically unclonable functions on FPGA. Informatika [Informatics], 2022, vol. 19, no. 4, pp. 27–41 (In Russ.).

23. Yarmolik V. N., Ivaniuk A. A. 2D physically unclonable functions of the arbiter type. Informatika [Informatics], 2023, vol. 20, no. 1, pp. 7–26 (In Russ.).

24. Yarmolik V. N., Ivaniuk A. A. Balanced arbiter physical uncloneable functions. Bezopasnost' informacionnyh tehnologij [IT Security], 2023, no. 1(30), pp. 92–107.

25. Yarmolik V. N. Kontrol’ i diagnostika vuchislitel’nuh system. Monitoring and Diagnostics of Computer Systems. Minsk, Bestprint, 2019, 387 p. (In Russ.).

26. Ogasahara Y., Hori Y., Katashita T., Iizuka T., Awano H., …, Koike H. Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. Integration, the VLSI Journal, 2020, vol. 71, pp. 144–153.

27. Hori Y., Kang H., Katashita T., Satoh A., Kawamura S., Kobara K. Evaluation of physical unclonable functions for 28-nm process field-programmable gate arrays. Journal of Information Processing, 2014, vol. 22, no. 2, pp. 344–356.