Creating and balancing the paths of arbiter-based physically unclonable functions on FPGA

Objectives. The problem of constructing a new structure of paths of physically unclonable function of the arbiter type (APUF) on the FPGA is being solved, based on the full use of internal resources of LUT-blocks, which are functionally repeaters. The relevance of the study is associated with the rapid development of physical cryptography tools. Another goal is the developing a methodology for eliminating the asymmetry of the APUF paths associated with the peculiarity of the synthesis of such circuits on the FPGA.
Methods. The methods of synthesis of digital devices, their parametric modeling and implementation on rapid prototyping boards are used. A ring oscillator circuit is used to measure the internal propagation delays of signals through the APUF paths.
Results. A new structure of the basic element of APUF paths with the use of two functional repeaters is proposed. The necessity of balancing the delays of APUF paths is demonstrated. A technique has been developed to eliminate the asymmetry of signal propagation through APUF paths based on controlled delay lines. The disadvantages of classical approaches as an APUF arbitrator and the need for their modification are shown.
Conclusion. The proposed approach to build APUF paths has shown its viability and promise. An improvement in the characteristics of APUF constructed according to the proposed method, as well as a reduction in hardware costs during their implementation compared to classical APUF schemes, is experimentally confirmed. It seems promising to develop the described methodology for constructing the APUF to improve the structure of the arbiter.

1. Pappu, R. Physical One-Way Functions: PhD Thesis in Media Arts and Sciences. Cambridge, Massachusetts Institute of Technology, 2001, 154 p.

2. Yarmolik V. N., Vashinko Y. G. Physical unclonable functions. Informatika [Informatics], 2011, no. 2(30), pp. 92–103 (In Russ.).

3. Ivaniuk A. A., Zalivaka S. S. Physical cryptography and security of digital devices. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2019, no. 2(120), pp. 50–58 (In Russ.).

4. Yang J. , Yu X., Wei R. A low resource consumption Arbiter PUF improved switch component design for FPGA. Journal of Physics: Conference Series, 2022, vol. 2221, р. 012011.

5. Yarmolik V. N., Ivaniuk A. A. Arbiter physical unclonable functions with asymmetric pairs of paths. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2022, no. 20(4), рр. 71–79 (In Russ.).

6. Ivaniuk A. A. Synthesis of symmetric paths of arbiter physically unclonable function on FPGA. Informatika [Informatics], 2019, vol. 16, no. 2, pp. 99–108 (In Russ.).

7. Ishak M. H., Mispan M. S., Chiew W. Ya, Kamaruddin M. R., Korobkov M. A. Secure lightweight obfuscated delay-based physicalunclonable function design on FPGA. Bulletin of Electrical Engineering and Informatics, 2022, vol. 11, no. 2, pp. 1075–1083. https://doi.org/10.11591/eei.v11i2.3265

8. Shamyna A. Yu., Ivaniuk A. A. Investigation of the timing parameters of the arbiter-based physically unclonable function using a ring oscillator. Cifrovaya transformaciya [Digital Transformation], 2022, no. 1(28), pp. 27–38 (In Russ.).