Monitoring the reliability of integrated circuits protection against Trojans: encoding and decoding of combinational structures
https://doi.org/10.37661/1816-0301-2021-18-3-7-17
Abstract
Integrated circuits, systems on a chip are the key links in various industrial systems and state defense systems. The emergence of counterfeit integrated circuits, problems of piracy, overproduction, unauthorized interference in the design of microcircuit, hardware Trojans require the development of methods and means of their timely detection. Trojans can be introduced into the integrated circuits structure both on the development stage and during the production process, including the stages of specification, design, verification and manufacturing. The inclusion of additional elements in the integrated circuits structure jeopardizes the functional suitability and reliability of the system as a whole. For the purpose of hardware protection of projects, the methods of hardware coding are currently used.
The paper discusses the features and reliability of logical coding of combinational circuits. An algorithm for cracking the code of combinational circuits is proposed, based on the description of encoded structure by the resolution function and reducing the problem to SAT CNF. The initial data for decoding the structure of a digital device is the structural implementation of encoded circuit, obtained, for example, by reverse engineering (prototype design), as well as an activated physical sample of an integrated circuit, when into protected from unauthorized access memory the correct key value is loaded. This sample can be used as a black box model. The main idea of breaking a key is to solve a problem without research on a large interval of values of input and output variables.
About the Authors
L. A. Zolotorevich
Belarusian State University of Informatics and Radioelectronics
Russian Federation
Russian Federation
Lyudmila A. Zolotorevich - Cand. Sci. (Eng.), Assoc. Prof.
St. Р. Brovki, 6, Minsk, 220013
V. A. Ilyinkov
Belarusian State University of Informatics and Radioelectronics
Valery A. Ilyinkov - Cand. Sci. (Eng.), Assoc. Prof.
St. Р. Brovki, 6, Minsk, 220013
References
1. Zolotorevich L. A. Hardware protection of digital devices. Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitel'naja tehnika, informatika [Bulletin of Tomsk State University. Management, Computer Technology, Informatics], 2020, no. 50, рр. 69-78. https://doi.org/10.17223/19988605/50/9 (In Russ.).
2. Subramanyan P., Ray S., Malik S. Evaluating the security of logic encryption algorithms. 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, USA, 5-7May 2015. Washington, 2015, рр. 137-143.
3. Rajendran J., Sam M., Sinanoglu O., Karri R. Security analysis of integrated circuit camouflaging. ACM SIGSAC Conference on Computer & Communications Security, Berlin, Germany, 4-8 November 2013. Berlin, 2013, рр. 709-720.
4. Roy J. A., Koushanfar F., Markov I. L. EPIC: Ending piracy of integrated circuits. IEEE Computer, 2010, vol. 43. no. 10, рр. 30-38.
5. Yasin M., Rajendran J., Sinanoglu O., Karri R. On improving the security of logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, vol. 35, no. 9, рр. 1411-1424.
6. Rajendran J., Pino Y., Sinanoglu O., Karri R. Logic encryption: a fault analysis perspective. DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe, Dresden, Germany, March, 2012. Dresden, 2012, рр. 953-958.
7. Rajendran J., Zhang H., Zhang C., Rose G. S., Pino Y., ..., Karri R. Fault analysis-based logic encryption. IEEE Transactions on Computers, 2015, vol. 64, no. 2, рр. 410-424.
8. Dupuis S., Ba P., Natale G. D., Flottes M., Rouzeyre B. A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. 20h IEEE International On-Line Testing Symposium, Platja d'Aro, Catalunya, Spain, 7-9 July 2014. Platja d'Aro, 2014, рр. 49-54.
9. Plaza S. M., Markov I. L. Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, vol. 34. no. 6, рр. 961-971.
10. Lee Y.-W., Touba N. Improving logic obfuscation via logic cone analysis. Proceedings Latin-American Test Symposium, Puerto Vallarta, Mexico, 25-27March 2015. Puerto Vallarta, 2015, рр. 1-6.
11. Roy J. A., Koushanfar F., Markov I. L. Ending piracy of integrated circuits. IEEE Computer, 2010, vol. 43, no. 10, рр. 30-38.
12. Karousos N., Pexaras K., Karybali I. G., Kalligeros E. Weighted logic locking: a new approach for IC piracy protection. IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), Thessaloniki, Greece, 3-5 July 2017. Thessaloniki, 2017, рр. 221-226.
13. Zolotorevich L. A. Research of methods and means of project verification and test generation of MES. Sbornik nauchnyh trudov Vserossijskoj nauchno-tehnicheskoj konferencii "Problemy razrabotki perspektivnyh mikrojelektronnyh sistem" (MJeS-2006) [Collection of Scientific Papers of the All-Russian Scientific and Technical Conference "Problems of Development of Promising Microelectronic Systems" (MES-2006)]. In Stempkovskij A. L. (ed.). Moscow, Institut problem proektirovanija v mikrojelektronike Rossijskoj akademii nauk, 2006, рр. 163-168 (In Russ.).
14. Zolotorevich L. A. Project verification and construction of superchip tests at the RTL level. Automation and Remote Control. New York, Plenum Press, 2013, vol. 74, iss. 1, рр. 113-122.
Review
For citations:
Zolotorevich L.A., Ilyinkov V.A. Monitoring the reliability of integrated circuits protection against Trojans: encoding and decoding of combinational structures. Informatics. 2021;18(3):7-17. (In Russ.) https://doi.org/10.37661/1816-0301-2021-18-3-7-17
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