Preview

Informatics

Advanced search

Pseudoexhaustive memory testing based on March A type march tests

https://doi.org/10.37661/1816-0301-2020-17-2-54-70

Abstract

The relevance of testing of memory devices of modern computing systems is shown. The methods and algorithms for implementing test procedures based on classical March tests are analyzed. Multiple March tests are highlighted to detect complex pattern-sensitive memory faults. To detect them, the necessary condition that test procedures must satisfy to deal complex faults, is substantiated. This condition is in the formation of a pseudo-exhaustive test for a given number of arbitrary memory cells. We study the effectiveness of single and double application of tests like MATS ++, March C– and March A, and also give its analytical estimates for a different number of k ≤ 10 memory cells participating in a malfunction. The applicability of the mathematical model of the combinatorial problem of the coupon collector for describing multiple memory testing is substantiated. The values of the average, minimum, and maximum multiplicity of multiple tests are presented to provide an exhaustive set of binary combinations for a given number of arbitrary memory cells. The validity of analytical estimates is experimentally shown and the high efficiency of the formation of a pseudo-exhaustive coverage by tests of the March A type is confirmed.

About the Authors

V. N. Yarmolik
Belarusian State University of Informatics and Radioelectronics
Belarus

Vyacheslav N. Yarmolik, Dr. Sci. (Eng.), Professor

Minsk



I. Mrozek
Bialystok University of Technology
Poland

Ireneusz Mrozek, Dr., Lecture

Bialystok



S. V. Yarmolik
Belarusian State University of Informatics and Radioelectronics
Belarus

Svetlana V. Yarmolik, Cand. Sci. (Eng.)

Minsk



References

1. Wang L.-T., Wu C.-W., Wen X. VLSI Test Principles and Architectures: Design for Testability. Elsevier, 2006, 808 p.

2. Yarmolik V. N. Kontrol’ i diagnostika vuchislitel’nuh sistem. Monitoring and Diagnostics of Computer Systems. Minsk, Bestprint, 2019, 387 р. (in Russian).

3. Ivaniuk А. А. Proektirovanie vstraivaemuh cifrovuh ustroistv i sistem. Designing Embedded Digital Devices and Systems. Minsk, Bestprint, 2012, 338 р. (in Russian).

4. Yarmolik V. N., Mrozek I., Levancevich V. А. Pseudoischerpuvayuschee testirovanie zapominayuschih ustroistv na baze mnogokratnuch marshevyh testov [Pseudo-exhaustive storage testing based on multiple march tests]. Informatika [Informatics], 2018, no. 1(15), рр. 110–121 (in Russian).

5. Sharma A. K. Semiconductor Memories: Technology, Testing, and Reliability. London, John Wiley & Sons, 2002, 480 р.

6. Niggemeyer D., Redeker M., Otterstedt J. Integration of non-classical faults in standard march tests. Records of the IEEE International Workshop on Memory Technology, Design and Testing, San Jose, 1998, рр. 91–98.

7. Yarmolik V. N., Murashko I. А., Kummert А., Ivaniuk А. А. Nerazrushayuschee testirovanie zapominayuschih ustroistv. Non-Destructive Storage Testing. Minsk, Bestprint, 2005, 230 р. (in Russian).

8. Mrozek I. Multi-run Memory Tests for Pattern Sensitive Faults. Cham, Springer International Publishing AG, 2019, 135 p.

9. Goor A. J. Testing Semiconductor Memories, Theory and Practice. Chichester, John Wiley & Sons, 1991, 536 p.

10. Yarmolik S. V. Address sequences and backgrounds with different hamming distance for multiple run march tests. IEEE International Journal of Applied Mathematics and Computer Science, 2008, vol. 18, no. 3, рр. 329−339.

11. Sokol B., Yarmolik S. V. Address sequence for march tests to detect pattern sensitive faults. Proceedings of 3 rd IEEE International Workshop on Electronic Design Test and Applications (DELTA’06). Kuala Lumpur, Malaysia, 2006, рр. 354–357.

12. Sokol B., Mrozek I., Yarmolik V. N. Impact of the address changing on the detection of pattern sensitive faults. Information Processing and Security Systems. London, Springer Science + Business Media, Inc., 2005, рр. 217–226.

13. Yarmolik V. N., Yarmolik S. V. Adresnue posledovatel’nosti dlya mnogokratnogo testirovaniya OZU [Address sequences for repeated testing of RAM]. Informatika [Informatics], 2014, no. 3(39), рр. 92–103 (in Russian).

14. Mrozek I., Yarmolik V. N. Antirandom test vectors for BIST in Hardware / Software systems. Fundamenta Informaticae, 2012, no. 119, рр. 1–23.

15. Mrozek I., Yarmolik V. N. Iterative antirandom testing. Journal of Electronic Testing: Theory and Applications (JETTA), 2012, vol. 9, no. 3, рр. 251–266.


Review

For citations:


Yarmolik V.N., Mrozek I., Yarmolik S.V. Pseudoexhaustive memory testing based on March A type march tests. Informatics. 2020;17(2):54-70. (In Russ.) https://doi.org/10.37661/1816-0301-2020-17-2-54-70

Views: 589


Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.


ISSN 1816-0301 (Print)
ISSN 2617-6963 (Online)