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<article article-type="research-article" dtd-version="1.3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:lang="ru"><front><journal-meta><journal-id journal-id-type="publisher-id">inform</journal-id><journal-title-group><journal-title xml:lang="ru">Информатика</journal-title><trans-title-group xml:lang="en"><trans-title>Informatics</trans-title></trans-title-group></journal-title-group><issn pub-type="ppub">1816-0301</issn><issn pub-type="epub">2617-6963</issn><publisher><publisher-name>UIIP NASB</publisher-name></publisher></journal-meta><article-meta><article-id custom-type="elpub" pub-id-type="custom">inform-96</article-id><article-categories><subj-group subj-group-type="heading"><subject>Research Article</subject></subj-group><subj-group subj-group-type="section-heading" xml:lang="ru"><subject>ЛОГИЧЕСКОЕ ПРОЕКТИРОВАНИЕ</subject></subj-group><subj-group subj-group-type="section-heading" xml:lang="en"><subject>LOGICAL DESIGN</subject></subj-group></article-categories><title-group><article-title>ПРОЕКТИРОВАНИЕ КОНФИГУРИРУЕМОГО СДВИГОВОГО РЕГИСТРА С ЛИНЕЙНОЙ ОБРАТНОЙ СВЯЗЬЮ</article-title><trans-title-group xml:lang="en"><trans-title>DESIGNING CONFIGURABLE SHIFT REGISTER WITH A LINEAR FEEDBACK</trans-title></trans-title-group></title-group><contrib-group><contrib contrib-type="author" corresp="yes"><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Иванюк</surname><given-names>А. А.</given-names></name><name name-style="western" xml:lang="en"><surname>Ivaniuk</surname><given-names>A. A.</given-names></name></name-alternatives><email xlink:type="simple">ivaniuk@bsuir.by</email><xref ref-type="aff" rid="aff-1"/></contrib></contrib-group><aff xml:lang="ru" id="aff-1"><institution>Белорусский государственный университет информатики и радиоэлектроники,</institution><country>Russian Federation</country></aff><pub-date pub-type="collection"><year>2013</year></pub-date><pub-date pub-type="epub"><day>01</day><month>10</month><year>2016</year></pub-date><volume>0</volume><issue>3</issue><fpage>82</fpage><lpage>92</lpage><permissions><copyright-statement>Copyright &amp;#x00A9; Иванюк А.А., 2016</copyright-statement><copyright-year>2016</copyright-year><copyright-holder xml:lang="ru">Иванюк А.А.</copyright-holder><copyright-holder xml:lang="en">Ivaniuk A.A.</copyright-holder><license xml:lang="ru" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>Данная работа распространяется под лицензией Creative Commons Attribution 4.0.</license-p></license><license xml:lang="en" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>This work is licensed under a Creative Commons Attribution 4.0 License.</license-p></license></permissions><self-uri xlink:href="https://inf.grid.by/jour/article/view/96">https://inf.grid.by/jour/article/view/96</self-uri><abstract><p>Рассматривается методика проектирования конфигурируемого сдвигового регистра, для ко-торого возможно задание его разрядности в различных режимах функционирования. Предложенная схема сдвигового регистра с линейной обратной связью позволяет использовать его в качестве цик-лического сдвигового регистра, генератора М-последовательности, счетчика Джонсона и однока-нального сигнатурного анализатора. Приводится оценка аппаратурных затрат на реализацию кон-фигурируемого сдвигового регистра.</p></abstract><trans-abstract xml:lang="en"><p>A method for designing a configurable shift register is considered, which allows setting its capacity in various operation modes. The suggested shift register with a linear feedback can be used as a cyclic shift register, a generator of M-sequences, Johnson's counter and a single-channel signature analyzer. An assessment of the relevant hardware implementation expenses is given.</p></trans-abstract></article-meta></front><back><ref-list><title>References</title><ref id="cit1"><label>1</label><citation-alternatives><mixed-citation xml:lang="ru">VLSI Test Principles and Architecture / L.-T. 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