informИнформатикаInformatics1816-03012617-6963UIIP NASBinform-515Research ArticleЛОГИЧЕСКОЕ ПРОЕКТИРОВАНИЕLOGICAL DESIGNТЕСТИРОВАНИЕ ОЗУ НА ОСНОВЕ АДАПТИВНОГО СЖАТИЯ ВЫХОДНЫХ ДАННЫХЯрмоликС. В.ЯрмоликВ. Н.Белорусский государственный университет информатики и радиоэлектроникиRussian Federation20091910201803(23)2735Copyright © Ярмолик С.В., Ярмолик В.Н., 20182018Ярмолик С.В., Ярмолик В.Н.Ярмолик С.В., Ярмолик В.Н.Данная работа распространяется под лицензией Creative Commons Attribution 4.0.This work is licensed under a Creative Commons Attribution 4.0 License.https://inf.grid.by/jour/article/view/515

Предлагается новая концепция неразрушающего тестирования оперативных запоминающих устройств (ОЗУ) на базе адаптивного сжатия выходных данных. Данная концепция основывается на использовании характеристики ОЗУ на базе адаптивного сжатия выходных данных, получаемой путем суммирования по модулю два всех адресов ячеек памяти, которые содержат единичные значения. Показывается, что эта характеристика может быть использована в качестве эталонной сигнатуры при тестировании ОЗУ. Рассматриваются основные свойства предлагаемых новых неразрушающих тестов, основанных на применении адаптивного сжатия выходных данных.

ReferencesBardell, P.H. Built-In Self-Test for VLSI: pseudorandom techniques / P.H. Bardell, W. McAnney, J. Savir. – N.Y. : John Wiley&Sons, 1987. – 576 p.Bardell, P.H. Built-In Self-Test for VLSI: pseudorandom techniques / P.H. Bardell, W. McAnney, J. Savir. – N.Y. : John Wiley&Sons, 1987. – 576 p.Dekker, R. Realistic Built-In Self-Test for Static RAMs / R. Dekker, F. Beenker, L. Thijasen // IEEE Design and Test of Computers. – 1989. – Vol. 6, № 1. – P. 26–34.Dekker, R. Realistic Built-In Self-Test for Static RAMs / R. Dekker, F. Beenker, L. Thijasen // IEEE Design and Test of Computers. – 1989. – Vol. 6, № 1. – P. 26–34.Jain, S.K. Built-In Self-Testing of Embedded Memories / S.K. Jain, S.H. Stroud // IEEE Design and Test of Computers. – 1986. – Vol. 3, № 5. – P. 27–37.Jain, S.K. Built-In Self-Testing of Embedded Memories / S.K. Jain, S.H. Stroud // IEEE Design and Test of Computers. – 1986. – Vol. 3, № 5. – P. 27–37.Rajsuman, R. RAMBIST Builder: A Methodology for Automatic Built In Self-Test Design of Embedded RAMs / R. Rajsuman // IEEE International Workshop on Memory Technol-ogy, Design and Testing (MTDT'96) : Rec., Singapore, 13–14 Aug. 1996 / IEEE Computer Society. – Singapore, 1996. – P. 50–56.Rajsuman, R. RAMBIST Builder: A Methodology for Automatic Built In Self-Test Design of Embedded RAMs / R. Rajsuman // IEEE International Workshop on Memory Technol-ogy, Design and Testing (MTDT'96) : Rec., Singapore, 13–14 Aug. 1996 / IEEE Computer Society. – Singapore, 1996. – P. 50–56.Treuer, R. Buit-In Self-Diagnosis for Repairable Embedded RAMS / R. Treuer, V.K. Agarwal // IEEE Design and Test of Computer. – June 1993. – Vol.10, № 2. – P. 24–33.Treuer, R. Buit-In Self-Diagnosis for Repairable Embedded RAMS / R. Treuer, V.K. Agarwal // IEEE Design and Test of Computer. – June 1993. – Vol.10, № 2. – P. 24–33.Chen, T. Design of a Self-Testing and Self-Repairing Structure for Highly Hierarchical Ultra-Large Capacity Memory Chips / T. Chen, G. Sunada // IEEE Transactions on VLSI Systems. – 1993. – Vol. 1, № 2. – P. 88–97.Chen, T. Design of a Self-Testing and Self-Repairing Structure for Highly Hierarchical Ultra-Large Capacity Memory Chips / T. Chen, G. Sunada // IEEE Transactions on VLSI Systems. – 1993. – Vol. 1, № 2. – P. 88–97.Le, K.T. A Novel Approach for Testing Memories Using a Built-in Self Testing Tech-nique / K.L. Le, K.K. Saluja // Test Conference: proc. Int. Conf., Washington D.C., USA, Sep-tember 1986 / IEEE Computer Society. – Washington, USA, 1986. – P. 830–839.Le, K.T. A Novel Approach for Testing Memories Using a Built-in Self Testing Tech-nique / K.L. Le, K.K. Saluja // Test Conference: proc. Int. Conf., Washington D.C., USA, Sep-tember 1986 / IEEE Computer Society. – Washington, USA, 1986. – P. 830–839.Goor, A.J. Testing Semiconductor Memories, Theory and Practice / A.J. Goor. – UK, Chi¬chester : John Wiley & Sons, 1991. – 536 p.Goor, A.J. Testing Semiconductor Memories, Theory and Practice / A.J. Goor. – UK, Chi¬chester : John Wiley & Sons, 1991. – 536 p.Nicolaidis, M. Transparent BIST for RAMS / M. Nicolaidis // Proc. Int. Test Conference, Baltimore, USA, September 1992 / IEEE Computer Society. – Washington, USA, 1992. – P. 598–607.Nicolaidis, M. Transparent BIST for RAMS / M. Nicolaidis // Proc. Int. Test Conference, Baltimore, USA, September 1992 / IEEE Computer Society. – Washington, USA, 1992. – P. 598–607.Неразрушающее тестирование запоминающих устройств / В.Н. Ярмолик [и др.]. – Минск : Бестпринт, 2005. – 230 с.Неразрушающее тестирование запоминающих устройств / В.Н. Ярмолик [и др.]. – Минск : Бестпринт, 2005. – 230 с.Cockburn, B. Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs / B. Cockburn, Y.-F. Sat // Test Conference : proc. Int. Conf., Washington D.C., USA, October 1995 / IEEE Computer Society. – Washington, USA, 1995. – P. 23–32.Cockburn, B. Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs / B. Cockburn, Y.-F. Sat // Test Conference : proc. Int. Conf., Washington D.C., USA, October 1995 / IEEE Computer Society. – Washington, USA, 1995. – P. 23–32.Hellebrand, S. Symmetric Transparent BIST for RAMs / S. Hellebrand, Y.-J. Wundelich, V.N. Yarmolik // IEEE Design, Automation and Test in Europe Conference (DATE'99) : proc. Int. Conf., Munich, Germany, 9–12 March 1999 / ACM Special Interest Group on Design Automation. – N.Y., USA, 1999. – P. 702–707.Hellebrand, S. Symmetric Transparent BIST for RAMs / S. Hellebrand, Y.-J. Wundelich, V.N. Yarmolik // IEEE Design, Automation and Test in Europe Conference (DATE'99) : proc. Int. Conf., Munich, Germany, 9–12 March 1999 / ACM Special Interest Group on Design Automation. – N.Y., USA, 1999. – P. 702–707.Yarmolik, V.N. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs / S. Hellebrand, Y.-J. Wundelich, V.N. Yarmolik // IEEE Design, Automation and Test in Europe Conference (DATE'99) : proc. Int. Conf., Paris, France, 23–26 February 1998 / ACM Special Interest Group on Design Automation. – N.Y., USA, 1998. – P. 173–179.Yarmolik, V.N. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs / S. Hellebrand, Y.-J. Wundelich, V.N. Yarmolik // IEEE Design, Automation and Test in Europe Conference (DATE'99) : proc. Int. Conf., Paris, France, 23–26 February 1998 / ACM Special Interest Group on Design Automation. – N.Y., USA, 1998. – P. 173–179.Bushnell, M. Essential of electronic testing for digital, memory and mixed-signal VLSI circuits / M. Bushnell, A. Vishwani. – N.Y. : Kluwer Academic Publishers, 2001.Bushnell, M. Essential of electronic testing for digital, memory and mixed-signal VLSI circuits / M. Bushnell, A. Vishwani. – N.Y. : Kluwer Academic Publishers, 2001.Efficient Online and Offline Testing of Embedded DRAMs / S. Hellebrand [et al.] // IEEE Transactions on COMPUTERS. – 2002. – Vol. 51, № 7. – P. 801–809.Efficient Online and Offline Testing of Embedded DRAMs / S. Hellebrand [et al.] // IEEE Transactions on COMPUTERS. – 2002. – Vol. 51, № 7. – P. 801–809.Yarmolik, V. Built-In Self-Test and Diagnosis for Ram Based on Self-Adjusting Output Data Compression / V. Yarmolik, A.A. Ivaniuk, M. Krips // Design and Diagnostics of Electronic Circuits and Systems DDECS 2002 : proc. of Fifth Int. Workshop, Brno, Czech Re-public, 17–19 April 2002. – Czech Republic, 2002. – P. 360–363.Yarmolik, V. Built-In Self-Test and Diagnosis for Ram Based on Self-Adjusting Output Data Compression / V. Yarmolik, A.A. Ivaniuk, M. Krips // Design and Diagnostics of Electronic Circuits and Systems DDECS 2002 : proc. of Fifth Int. Workshop, Brno, Czech Re-public, 17–19 April 2002. – Czech Republic, 2002. – P. 360–363.

The authors declare that there are no conflicts of interest present.