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<article article-type="research-article" dtd-version="1.3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:lang="ru"><front><journal-meta><journal-id journal-id-type="publisher-id">inform</journal-id><journal-title-group><journal-title xml:lang="ru">Информатика</journal-title><trans-title-group xml:lang="en"><trans-title>Informatics</trans-title></trans-title-group></journal-title-group><issn pub-type="ppub">1816-0301</issn><issn pub-type="epub">2617-6963</issn><publisher><publisher-name>UIIP NASB</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.37661/1816-0301-2023-20-1-7-26</article-id><article-id custom-type="elpub" pub-id-type="custom">inform-1214</article-id><article-categories><subj-group subj-group-type="heading"><subject>Research Article</subject></subj-group><subj-group subj-group-type="section-heading" xml:lang="ru"><subject>ЗАЩИТА ИНФОРМАЦИИ И НАДЕЖНОСТЬ СИСТЕМ</subject></subj-group><subj-group subj-group-type="section-heading" xml:lang="en"><subject>INFORMATION PROTECTION AND SYSTEM RELIABILITY</subject></subj-group></article-categories><title-group><article-title>Двухмерные физически неклонируемые функции типа арбитр</article-title><trans-title-group xml:lang="en"><trans-title>2D physically unclonable functions of the arbiter type</trans-title></trans-title-group></title-group><contrib-group><contrib contrib-type="author" corresp="yes"><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Ярмолик</surname><given-names>В. Н.</given-names></name><name name-style="western" xml:lang="en"><surname>Yarmolik</surname><given-names>V. N.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Ярмолик Вячеслав Николаевич, доктор технических  наук, профессор</p><p>ул. П. Бровки, 6, Минск, 220013</p></bio><bio xml:lang="en"><p>Vyacheslav N. Yarmolik, D. Sc. (Eng.), Prof.</p><p>st. P. Brovki, 6, Minsk, 220013</p></bio><email xlink:type="simple">yarmolik10ru@yahoo.com</email><xref ref-type="aff" rid="aff-1"/></contrib><contrib contrib-type="author" corresp="yes"><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Иванюк</surname><given-names>А. А.</given-names></name><name name-style="western" xml:lang="en"><surname>Ivaniuk</surname><given-names>A. A.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Иванюк Александр Александрович, доктор технических наук, доцент, профессор кафедры информатики, заведующий совместной учебной лабораторией «СК хайникс мемори солюшенс Восточная Европа»</p><p>ул. П. Бровки, 6, Минск, 220013</p></bio><bio xml:lang="en"><p>Alexander A. Ivaniuk, D. Sc. (Eng.), Assoc. Prof., Prof. of Computer Science Department, Head of the Joint Educational Laboratory "SK Hynix Memory Solutions Eastern Europe"</p><p>st. P. Brovki, 6, Minsk, 220013</p></bio><email xlink:type="simple">ivaniuk@bsuir.by</email><xref ref-type="aff" rid="aff-1"/></contrib></contrib-group><aff-alternatives id="aff-1"><aff xml:lang="ru"><institution>Белорусский государственный университет  информатики и радиоэлектроники</institution></aff><aff xml:lang="en"><institution>State University of Informatics and Radioelectronics</institution></aff></aff-alternatives><pub-date pub-type="collection"><year>2023</year></pub-date><pub-date pub-type="epub"><day>29</day><month>03</month><year>2023</year></pub-date><volume>20</volume><issue>1</issue><fpage>7</fpage><lpage>26</lpage><permissions><copyright-statement>Copyright &amp;#x00A9; Ярмолик В.Н., Иванюк А.А., 2023</copyright-statement><copyright-year>2023</copyright-year><copyright-holder xml:lang="ru">Ярмолик В.Н., Иванюк А.А.</copyright-holder><copyright-holder xml:lang="en">Yarmolik V.N., Ivaniuk A.A.</copyright-holder><license xml:lang="ru" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>Данная работа распространяется под лицензией Creative Commons Attribution 4.0.</license-p></license><license xml:lang="en" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>This work is licensed under a Creative Commons Attribution 4.0 License.</license-p></license></permissions><self-uri xlink:href="https://inf.grid.by/jour/article/view/1214">https://inf.grid.by/jour/article/view/1214</self-uri><abstract><sec><title>Цели</title><p>Цели. Решается задача построения нового класса физически неклонируемых функций типа арбитр (АФНФ), основанного на различии задержек по входам многочисленных модификаций базового элемента путем увеличения как количества входов, так и топологии их подключения. Подобный подход позволяет строить двухмерные физически неклонируемые функции (2D-АФНФ), в которых в отличие от классических АФНФ запрос, формируемый для каждого базового элемента, выбирает пару путей не из двух возможных, а из большего их количества. Актуальность данного исследования связана с активным развитием физической криптографии. В работе преследуются следующие цели: построение базовых элементов АФНФ и их модификаций, разработка методики построения 2D-АФНФ. </p></sec><sec><title>Методы</title><p>Методы. Используются методы синтеза и анализа цифровых устройств, в том числе на программируемых логических интегральных схемах, основы булевой алгебры и схемотехники.  </p></sec><sec><title>Результаты</title><p>Результаты. Показано, что в классических АФНФ применяется стандартный базовый элемент, выполняющий две функции, а именно функцию выбора пары путей Select и функцию переключения путей Switch, которые за счет их совместного использования позволяют достичь высоких характеристик. В первую очередь это касается стабильности функционирования АФНФ, характеризующейся небольшим числом запросов, для которых ответ случайным образом принимает одно из двух возможных значений:  0 или 1. Предложены модификации базового элемента в части реализаций его функций Select и Switch. Приводятся новые структуры базового элемента с внесенными модификациями их реализаций, в том числе в части увеличения количества пар путей базового элемента, из которых путем запроса выбирается одна из них и конфигурации их переключений. Применение разнообразных базовых элементов позволяет улучшать основные характеристики АФНФ, а также нарушать регулярность их структуры, которая является главной причиной взлома АФНФ путем машинного обучения.</p></sec><sec><title>Заключение</title><p>Заключение. Предложенный подход к построению 2D-АФНФ, основанный на различии задержек сигналов через базовый элемент, показал свою работоспособность и перспективность. Экспериментально подтвержден эффект улучшения характеристик подобных ФНФ, и в первую очередь стабильности их функционирования. Перспективным представляется дальнейшее развитие идеи построения 2D-АФНФ, экспериментальное исследование их характеристик и устойчивости к различного рода атакам, в том числе с использованием машинного обучения. </p></sec></abstract><trans-abstract xml:lang="en"><sec><title>Objectives</title><p>Objectives. The problem of constructing a new class of physically unclonable functions of the arbiter type (APUF) is being solved, based on the difference in delay times for the inputs of numerous modifications of the base element, due to both an increase in the number of inputs and the topology of their connection. Such an  approach allows building two-dimensional physically unclonable functions (2D-APUF), in which, unlike  classical APUF, the challenge generated for each basic element selects a pair of paths not from two possible, but from a larger number of them. The relevance of such a study is associated with the active development of  physical cryptography. The following goals are pursued in the work: the construction of the basic elements of the APUF and their modifications, the development of a methodology for constructing 2D-APUF.</p></sec><sec><title>Methods</title><p>Methods. The methods of synthesis and analysis of digital devices are used, including those based on  programmable logic integrated circuits, the basics of Boolean algebra and circuitry. </p></sec><sec><title>Results</title><p>Results. It is shown that the classical APUF uses a standard basic element that performs two functions,  namely, the function of choosing a pair of paths Select and the function of switching paths Switch, which, due to their joint use, allow achieving high performance. First of all, this concerns the stability of the APUF functioning, which is characterized by a small number of challenge, for which the response randomly takes one of two  possible values 0 or 1. Modifications of the base element in terms of the implementations of its Select and Switch functions are proposed. New structures of the base element are presented in which the modifications of their  implementations are made, including in terms of increasing the number of pairs of paths of the base element from which one of them is selected by the challenge, and the configurations of their switching. The use of  various basic elements makes it possible to improve the main characteristics of APUF, as well as to break the regularity of their structure, which was the main reason for hacking APUF through machine learning. </p></sec><sec><title>Conclusion</title><p>Conclusion. The proposed approach to the construction of physically unclonable 2D-APUF functions, based on the difference in signal delays through the base element, has shown its efficiency and promise. The effect of improving the characteristics of such PUFs has been experimentally confirmed with noticeable improvement in the stability of their functioning. It seems promising to further develop the ideas of constructing two-dimensional physically unclonable functions of the arbiter type, as well as experimental study of their characteristics, as well as resistance to various types of attacks, including using machine learning.</p></sec></trans-abstract><kwd-group xml:lang="ru"><kwd>физическая криптография</kwd><kwd>физически неклонируемые функции</kwd><kwd>физические однонаправленные функции</kwd><kwd>физически неклонируемые функции типа арбитр</kwd></kwd-group><kwd-group xml:lang="en"><kwd>physical cryptography</kwd><kwd>physically unclonable functions</kwd><kwd>physical one-way functions</kwd><kwd>physically unclonable arbiter-type functions</kwd></kwd-group><funding-group><funding-statement xml:lang="ru">Авторы выражают искреннюю благодарность резиденту ПВТ компании «СК хайникс мемори солюшенс Восточная Европа» за предоставленное оборудование для проведения экспериментов в рамках работы совместной учебной лаборатории с Белорусским государственным университетом информатики и радиоэлектроники.</funding-statement><funding-statement xml:lang="en">The authors express their sincere gratitude to the HTP resident of the "SK hynix memory solutions Eastern Europe" company for the equipment provided for carrying out experiments within the  framework of the joint laboratory with the Belarusian State University of Informatics and Radioelectronics.</funding-statement></funding-group></article-meta></front><back><ref-list><title>References</title><ref id="cit1"><label>1</label><citation-alternatives><mixed-citation xml:lang="ru">Pappu, R. Physical One-Way Functions: PhD Thesis in Media Arts and Sciences / R. Pappu. – Cambridge : Massachusetts Institute of Technology, 2001. – 154 p.</mixed-citation><mixed-citation xml:lang="en">Pappu R. Physical One-Way Functions: PhD Thesis in Media Arts and Sciences. Cambridge, Massachusetts Institute of Technology, 2001, 154 p.</mixed-citation></citation-alternatives></ref><ref id="cit2"><label>2</label><citation-alternatives><mixed-citation xml:lang="ru">Silicon physical random functions / B. Gassend [et al.] // Proc. of 9th Computer and Communications Security Conf. (CCS’02), Washington, DC USA, 18–22 Nov. 2002. – Washington, 2002. – P. 148–160.</mixed-citation><mixed-citation xml:lang="en">Gassend B., Clarke D., Dijk M. S., Devadas S. Silicon physical random functions. Proceedings of the 9th Computer and Communications Security Conference (CCS’02), Washington, DC USA, 18–22 November 2002. Washington, 2002, pp. 148–160.</mixed-citation></citation-alternatives></ref><ref id="cit3"><label>3</label><citation-alternatives><mixed-citation xml:lang="ru">Tuyls, P. Security with Noisy Data: On Private Biometrics, Secure Key Storage and Anti-Counterfeiting / P. Tuyls, B. Skoric, T. Kevenaar ; ed.: P. Tuyls. – N. Y. : Springer, 2007. – 339 p.</mixed-citation><mixed-citation xml:lang="en">Tuyls P., Skoric B., Kevenaar T. Security with Noisy Data: On Private Biometrics, Secure Key Storage and Anti-Counterfeiting. In P. Tuyls (ed.). New York, Springer, 2007, 339 p.</mixed-citation></citation-alternatives></ref><ref id="cit4"><label>4</label><citation-alternatives><mixed-citation xml:lang="ru">Rührmair, U. Strong PUFs: models, constructions, and security proofs / U. Rührmair, H. Busch, S. Katzenbeisser // Towards Hardware-Intrinsic Security / eds.: A.-R. Sadeghi, D. Naccache. – Berlin, Heidelberg : Springer, 2010. – P. 79–96.</mixed-citation><mixed-citation xml:lang="en">Rührmair U., Busch H., Katzenbeisser S. Strong PUFs: models, constructions, and security proofs. Towards Hardware-Intrinsic Security. In A.-R. Sadeghi, D. Naccache (eds.). Berlin, Heidelberg, Springer, 2010, pp. 79–96.</mixed-citation></citation-alternatives></ref><ref id="cit5"><label>5</label><citation-alternatives><mixed-citation xml:lang="ru">Skoric, B. Robust key extraction from physical uncloneable functions / B. Skoric, P. Tuyls, W. Ophey // Proc. of Intern. Conf. Applied Cryptography and Network Security, N. Y., USA, 7–10 June 2005. – N. Y., 2005. – P. 407–422.</mixed-citation><mixed-citation xml:lang="en">Skoric B., Tuyls P., Ophey W. Robust key extraction from physical uncloneable functions. Proceedings of International Conference Applied Cryptography and Network Security, New York, USA, 7–10 June 2005. New York, 2005, pp. 407–422.</mixed-citation></citation-alternatives></ref><ref id="cit6"><label>6</label><citation-alternatives><mixed-citation xml:lang="ru">A technique to build a secret key in integrated circuits for identification and authentication applications / J. W. Lee [et al.] // Proc. of Intern. Symp. VLSI Circuits (VLSI’04), Honolulu, Hawaii, USA, 7–19 June 2004. – Honolulu, 2004. – P. 176–179.</mixed-citation><mixed-citation xml:lang="en">Lee J. W., Lim D., Gassend B., Suh G. E., …, Devadas S. A technique to build a secret key in integrated circuits for identification and authentication applications. Proceedings of International Symposium VLSI Circuits (VLSI’04), Honolulu, Hawaii, USA, 7–19 June 2004. Honolulu, 2004, рр. 176–179.</mixed-citation></citation-alternatives></ref><ref id="cit7"><label>7</label><citation-alternatives><mixed-citation xml:lang="ru">Extracting secret keys from integrated circuits / D. Lim [et al.] // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. – 2005. – Vol. 13, no. 10. – P. 1200–1205.</mixed-citation><mixed-citation xml:lang="en">Lim D., Lee J. W., Gassend B., Suh G. E., …, Devadas S. Extracting secret keys from integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, vol. 13, no. 10, pp. 1200–1205.</mixed-citation></citation-alternatives></ref><ref id="cit8"><label>8</label><citation-alternatives><mixed-citation xml:lang="ru">Maes, R. PUFKY: A fully functional PUF-based cryptographic key generator / R. Maes, A. van Herrewege, I. Verbauwhede // Proc. of 14th Intern. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2012), Leuven, Belgium, 9–12 Sept. 2012. – Leuven, 2012. – P. 302–319.</mixed-citation><mixed-citation xml:lang="en">Maes R., Van Herrewege A., Verbauwhede I. PUFKY: A fully functional PUF-based cryptographic key generator. Proceedings of 14th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2012), Leuven, Belgium, 9–12 September 2012. Leuven, 2012, pp. 302–319.</mixed-citation></citation-alternatives></ref><ref id="cit9"><label>9</label><citation-alternatives><mixed-citation xml:lang="ru">Ярмолик, В. Н. Физически неклонируемые функции / В. Н. Ярмолик, Ю. Г. Вашинко // Информатика. – 2011. – № 2(30). – С. 92–103.</mixed-citation><mixed-citation xml:lang="en">Yarmolik V. N., Vashinko Y. G. Physical unclonable functions. Informatika [Informatics], 2011, no. 2(30), pp. 92–103 (In Russ.).</mixed-citation></citation-alternatives></ref><ref id="cit10"><label>10</label><citation-alternatives><mixed-citation xml:lang="ru">Иванюк, А. А. Физическая криптография и защита цифровых устройств / А. А. Иванюк, С. С. Заливако // Доклады БГУИР. – 2019. – № 2(120). – С. 50–58.</mixed-citation><mixed-citation xml:lang="en">Ivaniuk A. A., Zalivaka S. S. Physical cryptography and security of digital devices. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2019, no. 2(120), pp. 50–58 (In Russ.).</mixed-citation></citation-alternatives></ref><ref id="cit11"><label>11</label><citation-alternatives><mixed-citation xml:lang="ru">Программная реализация физически неклонируемых функций / Г. А. Мартвель [и др.] // Труды МФТИ. – 2020. – Т. 12, № 2. – C. 55–63.</mixed-citation><mixed-citation xml:lang="en">Martvel G. A., Chuprakov F. M., Nedostoev K. A., Baburin N. S. Software implementation of physically non-cloneable functions. Trudy Moskovskogo fiziko-tehnicheskogo instituta [Proceedings of Moscow Institute of Physics and Technology], 2020, vol. 12, no. 2, pp. 55–63 (In Russ.).</mixed-citation></citation-alternatives></ref><ref id="cit12"><label>12</label><citation-alternatives><mixed-citation xml:lang="ru">Rührmair, U. On the foundations of Physical Unclonable Functions / U. Rührmair, J. Sölter, F. Sehnke // IACR Cryptology ePrint Archive. – 2009. – Vol. 2009. – 20 p.</mixed-citation><mixed-citation xml:lang="en">Rührmair U., Sölter J., Sehnke F. On the foundations of Physical Unclonable Functions. IACR Cryptology ePrint Archive, 2009, vol. 2009, 20 p.</mixed-citation></citation-alternatives></ref><ref id="cit13"><label>13</label><citation-alternatives><mixed-citation xml:lang="ru">Delvaux, J. Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise / J. Delvaux, I. Verbauwhede // Proc. of IEEE Intern. Symp. on Hardware-Oriented Security and Trust (HOST), Austin, TX, USA, 2–3 June 2013. – Austin, 2013. – P. 137–142.</mixed-citation><mixed-citation xml:lang="en">Delvaux J., Verbauwhede I. Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise. Proceedings of IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Austin, TX, USA, 2–3 June 2013. Austin, 2013, pp. 137–142.</mixed-citation></citation-alternatives></ref><ref id="cit14"><label>14</label><citation-alternatives><mixed-citation xml:lang="ru">PUF modeling attacks on simulated and silicon data / U. Rührmair [et al.] // IEEE Transactions on Information Forensics and Security. – 2013. – Vol. 11, no. 8. – P. 1876–1891.</mixed-citation><mixed-citation xml:lang="en">Rührmair U., Sölter J., Sehnke F., Xu X., Mahmoud A., …, Devadas S. PUF modeling attacks on simulated and silicon data. IEEE Transactions on Information Forensics and Security, 2013, vol. 11, no. 8, pp. 1876–1891.</mixed-citation></citation-alternatives></ref><ref id="cit15"><label>15</label><citation-alternatives><mixed-citation xml:lang="ru">Xu, X. Using statistical models to improve the reliability of delay-based PUFs / X. Xu, W. Burleson, D. E. Holcomb // Proc. of IEEE Computer Society Annual Symp. on VLSI, Pittsburgh, PA, USA, 11–13 July 2016. – Pittsburgh, 2016. – P. 547–552.</mixed-citation><mixed-citation xml:lang="en">Xu X., Burleson W., Holcomb D. E. Using statistical models to improve the reliability of delay-based PUFs. Proceedings of IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, 11–13 July 2016. Pittsburgh, 2016, pp. 547–552.</mixed-citation></citation-alternatives></ref><ref id="cit16"><label>16</label><citation-alternatives><mixed-citation xml:lang="ru">Agarwal, A. Statistical timing analysis for intra-die process variations with spatial correlations / A. Agarwal, D. Blaauw, V. Zolotov // Proc. of Intern. Conf. on Computer Aided Design (ICCAD03), San Jose, CA, USA, 9–13 Nov. 2003. – San Jose, 2003. – P. 900–907.</mixed-citation><mixed-citation xml:lang="en">Agarwal A., Blaauw D., Zolotov V. Statistical timing analysis for intra-die process variations with spatial correlations. Proceedings of International Conference on Computer Aided Design (ICCAD03), San Jose, CA, USA, 9–13 November 2003. San Jose, 2003, pp. 900–907.</mixed-citation></citation-alternatives></ref><ref id="cit17"><label>17</label><citation-alternatives><mixed-citation xml:lang="ru">Клыбик, В. П. Метод увеличения стабильности физически неклонируемой функции типа «арбитр» / В. П. Клыбик, С. С. Заливако, А. А. Иванюк // Информатика. – 2017. − № 1(53). – С. 31–43.</mixed-citation><mixed-citation xml:lang="en">Klybik V. P., Zalivaka S. S., Ivaniuk A. A. Reliability enhancement method for "arbiter" physicaly unclonable function. Informatika [Informatics], 2017, no. 1(53), pp. 31–43 (In Russ.).</mixed-citation></citation-alternatives></ref><ref id="cit18"><label>18</label><citation-alternatives><mixed-citation xml:lang="ru">Ярмолик, В. Н. Физически неклонируемые функции с управляемой задержкой распространения сигналов / В. Н. Ярмолик, А. А. Иванюк, Н. Н. Шинкевич // Информатика. – 2022. − Т. 19, № 1. – С. 32–49.</mixed-citation><mixed-citation xml:lang="en">Yarmolik V. N., Ivaniuk A. A., Shynkevich N. N. Physically unclonable functions with controlled propagation delay. Informatika [Informatics], 2022, vol. 19, no. 1, pp. 32−49 (In Russ.).</mixed-citation></citation-alternatives></ref><ref id="cit19"><label>19</label><citation-alternatives><mixed-citation xml:lang="ru">Morozov, S. An analysis of delay based PUF implementations on FPGA / S. Morozov, A. Maiti, P. Schaumont // Proc. of Intern. Symp. on Applied Reconfigurable Computing: Tools and Applications (ARC 2010), Los Angeles, CA, US, 25–27 Mar. 2010. – Los Angeles, 2010. – P. 382–387.</mixed-citation><mixed-citation xml:lang="en">Morozov S., Maiti A., Schaumont P. An analysis of delay based PUF implementations on FPGA. Proceedings of International Symposium on Applied Reconfigurable Computing: Tools and Applications (ARC 2010), Los Angeles, CA, US, 25–27 March 2010. Los Angeles, 2010, pp. 382–387.</mixed-citation></citation-alternatives></ref><ref id="cit20"><label>20</label><citation-alternatives><mixed-citation xml:lang="ru">FPGA implementation of a cryptographically-secure PUF based on learning parity with noise / C. Jin [et al.] // Cryptography. – 2017. – Vol. 23, no. 1. – P. 1–20.</mixed-citation><mixed-citation xml:lang="en">Jin C., Herder C., Ren L., Nguyen P. H., Fuller B., …, Dijk M. van. FPGA implementation of a cryptographically-secure PUF based on learning parity with noise. Cryptography, 2017, vol. 23, no. 1, pp. 1–20.</mixed-citation></citation-alternatives></ref><ref id="cit21"><label>21</label><citation-alternatives><mixed-citation xml:lang="ru">Gu, C. Improved reliability of FPGA-based PUF identification generator design / C. Gu, N. Hanley, M. O’neil // ACM Transactions on Reconfigurable Technology and Systems. – 2017. – Vol. 10, no. 3. – P. 1–23.</mixed-citation><mixed-citation xml:lang="en">Gu C., Hanley N., O’neil M. Improved reliability of FPGA-based PUF identification generator design. ACM Transactions on Reconfigurable Technology and Systems, 2017, vol. 10, no. 3, pp. 1–23.</mixed-citation></citation-alternatives></ref><ref id="cit22"><label>22</label><citation-alternatives><mixed-citation xml:lang="ru">Kumar, A. METAPUF a challenge response pair generator / A. Kumar, S. L. Tripathi, R. Mishra // Periodicals of Engineering and Natural Sciences (PEN) . – 2018. – Vol. 2, no. 6. – P. 58–63.</mixed-citation><mixed-citation xml:lang="en">Kumar A., Tripathi S. L., Mishra R. METAPUF a challenge response pair generator. Periodicals of Engineering and Natural Sciences (PEN), 2018, vol. 2, no. 6, pp. 58–63.</mixed-citation></citation-alternatives></ref><ref id="cit23"><label>23</label><citation-alternatives><mixed-citation xml:lang="ru">Ozturk, E. Physical unclonable function with tristate buffers / E. Ozturk, G. Hammouri, B. Sunar // Proc. of IEEE Intern. Symp. on Circuits and Systems (ISCAS 2008), Seattle, Washington, USA, 18–21 May 2008. – Seattle, 2008. – P. 3194–3197.</mixed-citation><mixed-citation xml:lang="en">Ozturk E., Hammouri G., Sunar B. Physical unclonable function with tristate buffers. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, Washington, USA, 18–21 May 2008. Seattle, 2008, pp. 3194–3197.</mixed-citation></citation-alternatives></ref><ref id="cit24"><label>24</label><citation-alternatives><mixed-citation xml:lang="ru">Böhm, C. Physical Unclonable Functions in Theory and Practice / C. Böhm, M. Hofer. – N. Y. : Springer Science + Business Media, 2013. – 270 p.</mixed-citation><mixed-citation xml:lang="en">Böhm C., Hofer M. Physical Unclonable Functions in Theory and Practice. New York, Springer Science + Business Media, 2013, 270 p.</mixed-citation></citation-alternatives></ref><ref id="cit25"><label>25</label><citation-alternatives><mixed-citation xml:lang="ru">Ярмолик, В. Н. Физически неклонируемые функции типа арбитр с заведомо асимметричными парами путей / В. Н. Ярмолик, А. А. Иванюк // Доклады БГУИР. – 2022. – Т. 20, № 4. – С. 71–79.</mixed-citation><mixed-citation xml:lang="en">Yarmolik V. N., Ivaniuk A. A. Arbiter physical unclonable functions with asymmetric pairs of paths. Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki [Reports of the Belarusian State University of Informatics and Radioelectronics], 2022, vol. 20, no. 4, pp. 71–79 (In Russ.).</mixed-citation></citation-alternatives></ref><ref id="cit26"><label>26</label><citation-alternatives><mixed-citation xml:lang="ru">A new Arbiter PUF for enhancing unpredictability on FPGA / T. Machida [et al.] // The Scientific World Journal. – 2015. – Vol. 2015, art. ID 864812. – 13 p.</mixed-citation><mixed-citation xml:lang="en">Machida T., Yamamoto D., Iwamoto M., Sakiyama K. A new Arbiter PUF for enhancing unpredictability on FPGA. The Scientific World Journal, 2015, vol. 2015, art. ID 864812, 13 p.</mixed-citation></citation-alternatives></ref><ref id="cit27"><label>27</label><citation-alternatives><mixed-citation xml:lang="ru">Zhou, C. Secure and reliable XOR arbiter PUF design: An experimental study based on 1 trillion challenge response pair measurements / C. Zhou, K. K. Parhi, C. H. Kim // Proc. of 54th ACM/EDAC/IEEE Design Automation Conf. (DAC 2017), Austin, TX, USA, 18–22 June 2017. – Austin, 2017. – P. 1–6.</mixed-citation><mixed-citation xml:lang="en">Zhou C., Parhi K. K., Kim C. H. Secure and reliable XOR arbiter PUF design: An experimental study based on 1 trillion challenge response pair measurements. Proceedings of 54th ACM/EDAC/IEEE Design Automation Conference (DAC 2017), Austin, TX, USA, 18–22 June 2017. Austin, 2017, pp. 1–6.</mixed-citation></citation-alternatives></ref><ref id="cit28"><label>28</label><citation-alternatives><mixed-citation xml:lang="ru">Maiti, A. A systematic method to evaluate and compare the performance of Physical Unclonable Functions / A. Maiti, V. Gunreddy, P. Schaumont ; eds.: P. Athanas, D. Pnevmatikatos, N. Sklavos // Embedded Systems Design with FPGAs. – N. Y., Springer, 2013. – P. 245–267.</mixed-citation><mixed-citation xml:lang="en">Maiti A., Gunreddy V., Schaumont P. A systematic method to evaluate and compare the performance of Physical Unclonable Functions. In P. Athanas, D. Pnevmatikatos, N. Sklavos (eds.). Embedded Systems Design with FPGAs. New York, Springer, 2013, pp. 245–267.</mixed-citation></citation-alternatives></ref></ref-list><fn-group><fn fn-type="conflict"><p>The authors declare that there are no conflicts of interest present.</p></fn></fn-group></back></article>
